AM186CC-50KC\W C AMD, AM186CC-50KC\W C Datasheet - Page 40

• Manufacturer Part Number: AM186CC-50KC\W C
• Manufacturer: AMD

CLOCK GENERATION AND CONTROL
The Am186CC controller clocks include the general
system clock (CLKOUT), USB clock, transmitter/
receiver clocks for each HDLC channel, and the baud
rate generator clock for UART and High-Speed UART.
The SSI and the timers (Timers 0, 1, and 2) derive their
clocks from the system clock.
Features
The Am186CC controller clocks include the following
features and characteristics:
n Two independent crystal-controlled oscillators that
n Two independent internal PLLs, one of which
n Single clock source operation possible by sharing
n Each HDLC receives its clock inputs directly from
n SSI clock (SCLK) is derived from the system clock,
n Timers 0 and 1 can be configured to be driven by
n UART clock can be derived from the internal system
See Figure 8 on page 41 for a diagram of the basic
clock generation and Figure 9 on page 42 for
suggested clock frequencies and modes.
System Clock
The system PLL generates frequencies from 16 to
50 MHz. The reference for the system PLL can vary
40
use exter nal fundamental mode cr ystals or
oscillators to generate the system input clock and
the USB input clock.
generates a system clock (CLKOUT) that is 1x, 2x,
or 4x the system input clock, and one that generates
the 48-MHz clock required for the USB from either
a 48-, 24-, or 12-MHz input.
the clock source between the system and the USB.
the external communication clock pins (TCLK _X
and RCLK_X) in all modes except in GCI mode. In
GCI mode the external GCI communication clocks
(TCLK_A and RCLK_A) are first converted to an in-
ternal clocking format (analogous to PCM Highway)
before presentation to the HDLC. The system clock
must be at least the same frequency as any HDLC
clock.
– HDLC DCE mode supports clocks up to 10 MHz.
– HDLC PCM mode supports clocks up to 10 MHz.
– HDLC GCI mode supports a 1.536-MHz clock
divided by 2, 4, 8, 16, 32, 64, 128, or 256.
the timer input pins (TMRIN1, TMRIN0) or at one-
fourth of the system clock. Timer 2 is driven at one-
fourth of the system clock.
clock frequency or from the UART clock (UCLK)
input.
input. (System clock must be at least twice the
GCI clock.)
Am186™CC Communications Controller Data Sheet
from 8 to 40 MHz, depending on the PLL mode
selected and the desired system frequency (see
Figure 9 on page 42).
The system PLL modes are chosen by the state of the
{CLKSEL1} and {CLKSEL2} pins during reset. For
thes e pins trap se ttings see Table 31 , “Res et
Configuration Pins (Pinstraps),” on page A-10.
The system clock can be generated in one of two ways:
n Using the internal PLL running at 1x, 2x, or 4x the
n Bypassing the internal PLL. The external reference
USB Clock
The USB PLL provides the 48-MHz clock that is
required for USB full-speed operation. This clock is
divided down to provide a 12-MHz clock that supports
the full-speed USB rate (12 Mbit/s). The low-speed rate
of 1.5 Mbit/s is not supported. The USB PLL modes are
chosen by the state of the {USBSEL1} and {USBSEL2}
pins during reset. For these pinstrap settings, refer to
Table 31, “Reset Configuration Pins (Pinstraps),” on
page A-10.
The USB clock can be generated in one of two ways:
n Using the system clock. In this mode, the system
Note: When using the system clock for the USB clock
source, the designer must externally pull down the
USBX1 input.
n Using its own internal 48-MHz PLL. This PLL can
Note: The system clock must be a minimum of 24
MHz when using the USB peripheral controller and its
internal 48-MHz PLL.
The USB specification requires a frequency tolerance
of less than 2500 ppm, which must be met whether
using an external clock source, a crystal on USBX1–
USBX2, or clock sharing by system and USB. When
using a crystal, some frequency tolerance margin must
be allowed to account for the differences in external
loading capacitances, etc. The usual rule of thumb is to
specify a crystal with a frequency tolerance of one half
the required frequency tolerance.
reference clock. The reference clock can be
generated from an external crystal using the
integrated oscillator or an external oscillator input.
generated from either a crystal or an external
oscillator input is used to generate the system clock.
For more information about bypassing the internal
PLL, refer to “PLL Bypass Mode” on page 43.
PLL is restricted to 48-MHz operation only.
run in 2x or 4x mode and requires a 12- or 24-MHz
reference that can be generated by either the
integrated cr ystal-controlled oscillator or an
external oscillator input.