MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 107
MT47H32M16HR-25E AIT:G
Manufacturer Part Number
MT47H32M16HR-25E AIT:G
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
Manufacturer
Micron
Datasheet
1.MT47H64M8CF-25E_ITG.pdf
(129 pages)
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Figure 62: Bank Write – with Auto Precharge
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
DQS, DQS#
Command
Bank select
Address
DQ 6
CK#
CKE
A10
DM
CK
NOP 1
T0
Notes:
Bank x
ACT
RA
T1
RA
t CK
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4 and AL = 0 in the case shown.
3. Enable auto precharge.
4. WR is programmed via MR9–MR11 and is calculated by dividing
5. Subsequent rising DQS signals must align to the clock within
6. DI n = data-in from column n; subsequent elements are applied in the programmed or-
7.
8.
these times.
rounding up to the next integer value.
der.
t
t
DSH is applicable during
DSS is applicable during
t RCD
NOP 1
T2
t CH
Micron Confidential and Proprietary
t CL
WRITE 2
Bank x
Col n
3
T3
WL ± t DQSS (NOM)
WL = 2
NOP 1
t
107
T4
t
DQSS (MAX) and is referenced from CK T6 or T7.
DQSS (MIN) and is referenced from CK T5 or T6.
512Mb: x8, x16 Automotive DDR2 SDRAM
t WPRE
NOP 1
T5
DI
Micron Technology, Inc. reserves the right to change products or specifications without notice.
n
t RAS
T5n
t DQSL t DQSH t WPST
NOP 1
5
T6
T6n
Transitioning Data
NOP 1
T7
2010 Micron Technology, Inc. All rights reserved.
t
DQSS.
t
WR (in ns) by
NOP 1
WR 4
T8
Don’t Care
NOP 1
t
T9
CK and
WRITE
t RP
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