MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 123

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

ODT Timing
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Once a 12ns delay (
bled via the EMR LOAD MODE command, ODT can be accessed under two timing cate-
gories. ODT will operate either in synchronous mode or asynchronous mode, depend-
ing on the state of CKE. ODT can switch anytime except during self refresh mode and a
few clocks after being enabled via EMR, as shown in Figure 78 (page 124).
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]),
Figure 80 (page 125).
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
t
ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-
rameter
nal satisfies
(MIN) is satisfied,
shows the example where
cur until state T3. When
ODT turn-on timing prior to entering any power-down mode is determined by the pa-
rameter
isfies
satisfied,
the example where
til state T3. When
ODT turn-off timing after exiting any power-down mode is determined by the parame-
ter
satisfies
satisfied,
example where
When
ODT turn-on timing after exiting either slow-exit power-down mode or precharge pow-
er-down mode is determined by the parameter
(page 129). At state Ta1, the ODT HIGH signal satisfies
er-down mode at state T1. When
rameters apply. Figure 85 (page 129) also shows the example where
satisfied because ODT HIGH occurs at state Ta0. When
t
AONPD and
AONPD timing parameters apply.
t
AXPD (MIN), as shown in Figure 84 (page 128). At state Ta1, the ODT LOW signal
t
ANPD (MIN) prior to entering power-down mode at T5. When
t
AXPD (MIN) is not satisfied,
t
t
t
ANPD (MIN), as shown in Figure 82 (page 126). At state T2, the ODT HIGH sig-
ANPD, as shown in Figure 83 (page 127). At state T2, the ODT HIGH signal sat-
AXPD (MIN) after exiting power-down mode at state T1. When
t
t
AOND and
AOFD and
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t
t
ANPD (MIN) prior to entering power-down mode at T5. When
AOND,
t
AOFPD timing parameters are applied, as shown in Figure 81 (page 126).
t
AXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0.
t
t
ANPD (MIN) is not satisfied,
AOFD and
t
t
MOD) has been satisfied, and after the ODT function has been ena-
ANPD (MIN) is not satisfied because ODT HIGH does not occur un-
t
t
AON,
t
AOF timing parameters apply. Figure 84 (page 128) also shows the
AON timing parameters apply. Figure 83 (page 127) also shows
t
ANPD (MIN) is not satisfied,
t
ANPD (MIN) is not satisfied because ODT HIGH does not oc-
t
AOFD, and
123
t
AOF timing parameters apply. Figure 82 (page 126) also
512Mb: x8, x16 Automotive DDR2 SDRAM
t
AXPD (MIN) is satisfied,
t
AOFPD timing parameters apply.
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
AOF timing parameters are applied, as shown in
t
t
AONPD timing parameters apply.
AXPD (MIN), as shown in Figure 85
t
t
AOFPD timing parameters apply.
AXPD (MIN) after exiting pow-
t
AXPD (MIN) is not satisfied,
t
AOND and
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t
AXPD (MIN) is not
t
ANPD (MIN) is
t
AON timing pa-
t
ODT Timing
AXPD (MIN) is
t
ANPD