MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 93

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

Figure 48: READ-to-PRECHARGE – BL = 4
Figure 49: READ-to-PRECHARGE – BL = 8
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
Notes:
lowing the PRECHARGE command, a subsequent command to the same bank cannot
be issued until
access of the last data elements.
Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 48 and in Figure 49
for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is AL + BL/2 -
DQS, DQS#
DQS, DQS#
Command
Command
2CK + MAX (
Address
Address
1. RL = 4 (AL = 1, CL = 3); BL = 4.
2.
3. Shown with nominal
1. RL = 4 (AL = 1, CL = 3); BL = 8.
2.
3. Shown with nominal
CK#
A10
CK#
A10
DQ
CK
DQ
CK
t
t
RTP
RTP
Bank a
Bank a
READ
READ
T0
T0
AL + BL/2 - 2CK + MAX ( t RTP/ t CK or 2CK)
2 clocks.
2 clocks.
Micron Confidential and Proprietary
AL = 1
AL = 1
t
RTP/
t
First 4-bit
prefetch
RP is met. However, part of the row precharge time is hidden during the
NOP
prefetch
AL + BL/2 - 2CK + MAX ( t RTP/ t CK or 2CK)
4-bit
T1
• t RAS (MIN)
NOP
T1
t
CK or 2 × CK) where MAX means the larger of the two.
•t RAS (MIN)
• t RTP (MIN)
NOP
T2
t
t
AC,
AC,
NOP
CL = 3
T2
Second 4-bit
93
t
t
DQSCK, and
DQSCK, and
CL = 3
512Mb: x8, x16 Automotive DDR2 SDRAM
prefetch
• t RC (MIN)
•t RC (MIN)
NOP
T3
Bank a
Valid
PRE
T3
•t RTP (MIN)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
T4
t
t
DO
DQSQ.
DQSQ.
NOP
T4
• t RP (MIN)
DO
DO
Bank a
Valid
PRE
T5
DO
DO
NOP
T5
Transitioning Data
Transitioning Data
DO
DO
NOP
T6
•t RP (MIN)
DO
DO
Bank a
Valid
ACT
T6
DO
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NOP
T7
DO
Don’t Care
Don’t Care
DO
NOP
T7
Bank a
Valid
ACT
T8
READ