AD668SQ883B Analog Devices, AD668SQ883B Datasheet
AD668SQ883B
Related parts for AD668SQ883B
AD668SQ883B Summary of contents
Page 1
... Furthermore, the output resistance of the DAC is trimmed to 100 Ω ± 1.0%. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use ...
Page 2
AD668–SPECIFICATIONS Parameter RESOLUTION LSB WEIGHT (At Nominal FSR) Current Voltage (Current into ACCURACY Linearity MIN MAX Differential Nonlinearity MIN MAX Monotonicity Unipolar Offset (Digital) Bipolar Offset Bipolar Zero Analog Offset ...
Page 3
Parameter AC CHARACTERISTICS Analog Settling Time (10% to 120% Step) to ± ± 0.1% to ± 0.025% Digital Settling Time Current to ± ± 0.025% Voltage (100 Ω Internal ...
Page 4
... Q = Cerdip. DEFINITIONS LINEARITY ERROR (also called INTEGRAL NONLINEAR- ITY OR INL): Analog Devices defines linearity error as the maximum deviation of the actual analog output from the ideal output (a straight line drawn from 0 to FS) for any bit combina- tion expressed in multiples of 1 LSB. The AD668 is laser trimmed to 1/4 LSB (0.006% of FS) maximum linearity error at +25° ...
Page 5
ANALOG OFFSET ERROR: The analog offset is defined as the offset of the analog amplifier channel, referred to the analog input. Ideally, this would be measured with the analog input and the digital input at full scale. ...
Page 6
AD668 V 0.1 < < 1 NOM 0 < < 0.1 constitutes an undervoltage condition and IN NOM is subject to the specified recovery time. 1.2 < constitutes an overvoltage condition. This can IN ...
Page 7
DIGITAL INPUT CONSIDERATIONS The AD668 uses a standard positive true straight binary code for unipolar outputs (all 1s full-scale output), and an offset bi- nary code for bipolar output ranges. In the bipolar mode, with all 0s on the inputs, ...
Page 8
AD668 – a 200 Ω resistor with one end internally wired to the out put pin 200 Ω ± 20% DAC output impedance is desired, R should be shorted Grounding R OUT output ...
Page 9
Figure 8. 1.25 V REFIN/ ± 500 mV Unbuffered Bipolar Output 5 V REFIN BIPOLAR, UNBUFFERED VOLTAGE OUTPUT Figure 9 demonstrates how a larger unbuffered voltage output swing can be realized. R (Pin 19) is tied to the ...
Page 10
AD668 Nominal Analog Input –500 mV to +500 mV Unipolar Bipolar 1 V Unbuffered V Unbuffered V OUT A = Pins Unipolar Bipolar Unbuffered V Unbuffered V OUT 1.25 ...
Page 11
While the two DACs are similar in many ways, the optimal decoupling schemes differ between the two parts and care should be used to insure that each is implemented appropriately. Figure 13. AD568 Driving the AD668 CONSTRUCTION GUIDELINES ...
Page 12
AD668 HIGH SPEED INTERCONNECT AND ROUTING It is essential that care be taken in the signal and power ground circuits to avoid inducing extraneous voltage drops in the signal ground paths suggested that all connections be short, di- ...
Page 13
Figure 18. Small Signal Bandwidth vs. DC Reference Level Noise Spectrum Figure 19 shows the noise spectrum of the DAC with all bits on. The noise floor of – just above the noise floor of the in- strument ...
Page 14
AD668 Figure 23. Settling Time Circuit Digital Settling Time vs. V REF The reference amplifier loop has been compensated for optimal settling performance 100%, but as Figure 24 REF NOM indicates, there is relatively little degradation ...
Page 15
DAC is not supposed to be changing codes. Data Skew The AD668, like many of its slower predecessors, essentially uses each ...
Page 16
AD668 Figure 28a. PCB Layout of Foil Side Figure 28b. PCB Layout of Component Side OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Cerdip (Suffix Q) –16– REV. A ...