IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 18

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
MPR Register Address Definition
The following Table provides an overview of the available data locations, how they are addressed by MR3 A[1:0] during a
MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.
MPR MR3 Register Definition
NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent
MPR Functional Description
NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
NOTE: Good reference for the example of MPR feature is the JEDEC standard No.93-3D, 4.10.4 Protocol example.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
MR3
A[2]
1b
1b
1b
1b




One bit wide logical interface via all DQ pins during READ operation.
Register Read on x16:
Addressing during for Multi Purpose Register reads for all MPR agents:
Regular interface functionality during register reads:
A[1:0]
MR3
00b
01b
10b
11b
o
o
o
o
o
o
o
o
o
o
o
o
o
o
DQL[0] and DQU[0] drive information from MPR.
DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b.
BA[2:0]: don’t care
A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4
cases, the burst order is switched on nibble base A[2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order:
4,5,6,7 *)
A[9:3]: don’t care
A10/AP: don’t care
A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
A11, A13, A14: don’t care
Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
Support of read burst chop (MRS and on-the-fly via A12/BC)
All other address bits (remaining column address bits including A10, all bank address bits) will be ignored
by the DDR3 SDRAM.
Regular read latencies and AC timings apply.
DLL must be locked prior to MPR Reads.
Read predefined pattern
for system Calibration
Function
RFU
RFU
RFU
Length
Burst
BC4
BC4
BC4
BC4
BC4
BC4
BC4
BC4
BL8
BL8
BL8
BL8
Read Address
A[2:0]
000b
000b
100b
000b
000b
100b
000b
000b
100b
000b
000b
100b
Burst Order and Data Pattern
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
Burst order 0,1,2,3
Pre-defined Data Pattern [0,1,0,1]
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3
Burst order 4,5,6,7
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3
Burst order 4,5,6,7
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3
Burst order 4,5,6,7
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