IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 70

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error
23. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage
ZQCorrection / [(TSens x Tdriftrate) + (VSens x Vdriftrate)]
, where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and
voltage sensitivities.
For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15mV/sec, then the interval
between ZQCS commands is calculated as
0.5 / [(1.5x1)+(0.15x15)] = 0.133  128ms
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of
28. Pulse width of a input signal is defined as the width between the first crossing of Vref(dc) and the consecutive
29. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from one falling
30. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured from one rising
31. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
32. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and
Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between
ZQCS commands can be determined from these tables and other application-specific parameters.
(Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. the interval could be defined by the
following formula:
falling edge.
rising edge.
derating to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier
reference point [(175mV - 150mV) / 1V/ns].
crossing of Vref(dc).
edge to the next consecutive rising edge.
edge to the next consecutive falling edge.
parameter in the application.
in the application.
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