IS46TR16128A-125KBLA1-TR ISSI, IS46TR16128A-125KBLA1-TR Datasheet - Page 35

• Manufacturer Part Number: IS46TR16128A-125KBLA1-TR
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
4.3.2.2 Allowed time before ringback (tDVAC) for CK - CK# and DQS - DQS#
4.3.3. Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK#, DQS#, DQSL#, or DQSU#) has also to
comply with certain requirements for single-ended signals.
CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH(ac) / VIL(ac) )
for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS#, DQSL# have to reach VSEHmin / VSELmax
(approximately the ac-levels (VIH(ac) / VIL(ac) ) for DQ signals) in every half-cycle preceding and following a valid
transition.
4.3.3.1. Single-ended levels for CK, DQS, DQSL, DQSU, CK#, DQS#, DQSL# or DQSU#
Notes:
1. For CK, CK# use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQS#, DQSL, DQSL#, DQSU, DQSU#) use VIH/VIL(ac) of DQs.
2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a
3.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Symbol
VSEH
VSEL
signal group, then the reduced level applies also here
These values are not defined, however the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the
respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Slew Rate [V/ns]
> 4.0
< 1.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended Low-level for CK, CK
Single-ended low-level for strobes
VDD or VDDQ
VSEHmin
VDD/2 or VDDQ/2
VSELmax
VSS or VSSQ
Parameter
Figure 4.3.3 Single-ended requirement for differential signals.
tDVAC [ps] @IVIH/Ldiff(ac)I = 350mV
min
75
57
50
38
34
29
22
13
0
0
max
(VDDQ/2) + 0.175
(VDDQ/2) + 0.175
-
-
-
-
-
-
-
-
-
-
VSEH
DDR3/DDR3L-800, 1066, 1333, & 1600
note3
note3
Min
tDVAC [ps] @IVIH/Ldiff(ac)I = 300mV
(VDDQ/2) - 0.175
(VDDQ/2) - 0.175
CK or DQS
VSEL
min
175
170
167
163
162
161
159
155
150
150
note3
note3
Max
time
Unit
V
V
V
V
max
-
-
-
-
-
-
-
-
-
-
35
Notes
1, 2
1, 2
1, 2
1, 2