dsPIC33FJ32GP102-I/SO Microchip Technology, dsPIC33FJ32GP102-I/SO Datasheet - Page 273

• Manufacturer Part Number: dsPIC33FJ32GP102-I/SO
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP102-I/SO

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: QFN-28
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

TABLE 24-2:
 2011-2012 Microchip Technology Inc.
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Base
Instr
#
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
MPY
MPY.N
MSC
MUL
NEG
NOP
POP
PUSH
PWRSAV
RCALL
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
RLNC
RRC
Mnemonic
Assembly
INSTRUCTION SET OVERVIEW (CONTINUED)
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MSC
MUL.SS
MUL.SU
MUL.US
MUL.UU
MUL.SU
MUL.UU
MUL
NEG
NEG
NEG
NEG
NOP
NOPR
POP
POP
POP.D
POP.S
PUSH
PUSH
PUSH.D
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
RLC
RLC
RLNC
RLNC
RLNC
RRC
RRC
RRC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,#lit5,Wnd
f
Acc
f
f,WREG
Ws,Wd
f
Wdo
Wnd
f
Wso
Wns
Expr
Wn
#lit14
Wn
#lit10,Wn
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
Assembly Syntax
#lit1
Multiply Wm by Wn to Accumulator
Square Wm to Accumulator
(Multiply Wm by Wn) to Accumulator
Multiply and Subtract from Accumulator
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
W3:W2 = f * WREG
Negate Accumulator
f = f + 1
WREG = f + 1
Wd = Ws + 1
No Operation
No Operation
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
Pop Shadow Registers
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
Push Shadow Registers
Go into Sleep or Idle mode
Relative Call
Computed Call
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software device Reset
Return from interrupt
Return with literal in Wn
Return from Subroutine
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
Description
Words
# of
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
3 (2)
3 (2)
3 (2)
DS70652E-page 273
# of
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
Status Flags
OA,OB,OAB,
OA,OB,OAB,
OA,OB,OAB,
OA,OB,OAB,
WDTO,Sleep
SA,SB,SAB
SA,SB,SAB
SA,SB,SAB
SA,SB,SAB
Affected
C,N,Z
C,N,Z
C,N,Z
C,N,Z
C,N,Z
C,N,Z
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
N,Z
N,Z
N,Z
All