dsPIC33FJ32GP102-I/SO Microchip Technology, dsPIC33FJ32GP102-I/SO Datasheet - Page 62

• Manufacturer Part Number: dsPIC33FJ32GP102-I/SO
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP102-I/SO

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: QFN-28
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

TABLE 4-12:
TABLE 4-13:
TABLE 4-14:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
SFR Name
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
SFR Name
Name
SFR
Addr
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0240
0242
0244
0248
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0220
0222
0224
0226
0228
SFR
SFR
Addr
0200
0202
0204
0206
0208
020A
020C
SFR
I2C1 REGISTER MAP
UART1 REGISTER MAP
SPI1 REGISTER MAP
UTXISEL1
FRMEN
ACKSTAT
SPIEN
UARTEN
Bit 15
I2CEN
Bit 15
Bit 15
—
—
—
—
—
—
—
—
SPIFSD
UTXINV UTXISEL0
TRSTAT
Bit 14
Bit 14
Bit 14
—
—
—
—
—
—
—
—
—
—
—
FRMPOL
I2CSIDL
SPISIDL
Bit 13
USIDL
Bit 13
Bit 13
—
—
—
—
—
—
—
—
—
SCLREL
DISSCK
Bit 12
IREN
Bit 12
Bit 12
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
RTSMD
DISSDO MODE16
Bit 11
IPMIEN
Bit 11
Bit 11
—
—
—
—
—
—
—
—
—
—
UTXEN
Bit 10
Bit 10
Bit 10
A10M
—
—
—
BCL
—
—
—
—
—
—
—
UTXBF
SPI1 Transmit and Receive Buffer Register
UEN1
Bit 9
DISSLW
GCSTAT
—
—
Bit 9
SMP
Bit 9
—
—
—
—
—
Baud Rate Generator Prescaler
UEN0
TRMT
Bit 8
Bit 8
ADD10
CKE
SMEN
Bit 8
—
—
—
—
WAKE
Bit 7
URXISEL<1:0>
SSEN
Bit 7
IWCOL
GCEN
Bit 7
—
—
LPBACK
SPIROV
Bit 6
Bit 6
STREN
CKP
I2COV
Bit 6
—
Address Mask Register
ABAUD
ADDEN
MSTEN
Bit 5
Bit 5
ACKDT
Baud Rate Generator Register
Address Register
UART Transmit Register
Bit 5
UART Receive Register
—
—
D_A
URXINV
RIDLE
Bit 4
Bit 4
ACKEN
Transmit Register
Receive Register
Bit 4
—
—
P
SPRE<2:0>
BRGH
PERR
Bit 3
Bit 3
RCEN
Bit 3
—
—
S
FERR
Bit 2
Bit 2
Bit 2
PEN
R_W
—
—
PDSEL<1:0>
FRMDLY
SPITBF
OERR
Bit 1
Bit 1
RSEN
Bit 1
RBF
PPRE<1:0>
URXDA
STSEL
SPIRBF
Bit 0
Bit 0
Bit 0
SEN
TBF
—
Resets
Resets
Resets
0000
0110
xxxx
0000
0000
0000
0000
0000
0000
0000
00FF
0000
1000
0000
0000
0000
All
All
All