dsPIC33FJ32GP102-I/SO Microchip Technology, dsPIC33FJ32GP102-I/SO Datasheet - Page 66

• Manufacturer Part Number: dsPIC33FJ32GP102-I/SO
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP102-I/SO

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: QFN-28
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

TABLE 4-18:
TABLE 4-19:
TABLE 4-20:
CTMUCON1 033A
CTMUCON2 033C
CTMUICON
Legend:
ALRMVAL
ALCFGRPT
RTCVAL
RCFGCAL
Legend:
PADCFG1
Legend:
File Name
File Name
File Name
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
033E
Addr
0620
0622
0624
0626
Addr
02FC
EDG1MOD EDG1POL
CTMU REGISTER MAP
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
PAD CONFIGURATION REGISTER MAP
ALRMEN
CTMUEN
RTCEN
Bit 15
Bit 15
Bit 15
—
CHIME
Bit 14
Bit 14
Bit 14
—
—
—
RTCWREN RTCSYNC HALFSEC
CTMUSIDL
Bit 13
Bit 13
Bit 13
—
ITRIM<5:0>
Bit 12
Bit 12
—
Bit 12
TGEN
EDG1SEL<3:0>
AMASK<3:0>
Bit 11
EDGEN EDGSEQEN
Bit 11
—
Bit 11
Bit 10
—
Bit 10
RTCOE
Bit 10
RTCC Value Register Window based on RTCPTR<1:0>
Alarm Value Register Window based on APTR<1:0>
Bit 9
—
EDG2STAT EDG1STAT EDG2MOD EDG2POL
IDISSEN
Bit 9
Bit 9
ALRMPTR<1:0>
RTCPTR<1:0>
IRNG<1:0>
Bit 8
—
CTTRIG
Bit 8
Bit 8
Bit 7
—
Bit 7
Bit 6
Bit 7
—
—
—
Bit 6
Bit 5
—
Bit 6
—
—
Bit 5
Bit 4
—
Bit 5
—
—
Bit 4
ARPT<7:0>
CAL<7:0>
Bit 3
EDG2SEL<3:0>
—
Bit 4
—
—
Bit 3
Bit 2
Bit 3
—
—
—
Bit 2
RTSECSEL
Bit 2
—
—
Bit 1
Bit 1
Bit 1
—
—
—
Bit 0
—
Bit 0
Bit 0
—
—
—
Resets
Resets
Resets
0000
xxxx
0000
xxxx
0000
0000
0000
0000
All
All
All