dsPIC33FJ32GP102-I/SO Microchip Technology, dsPIC33FJ32GP102-I/SO Datasheet - Page 90

• Manufacturer Part Number: dsPIC33FJ32GP102-I/SO
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP102-I/SO

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: QFN-28
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
6.2
The
dsPIC33FJ32(GP/MC)101/102/104 family of devices
have two types of Reset:
• Cold Reset
• Warm Reset
A Cold Reset is the result of a POR or a BOR. On a
Cold Reset, the FNOSC Configuration bits in the FOSC
Configuration register selects the device clock source.
TABLE 6-1:
DS70652E-page 90
FRC, FRCDIV16,
FRCDIVN
FRCPLL
MS
HS
EC
MSPLL
ECPLL
SOSC
LPRC
Note 1:
Oscillator Mode
2:
3:
System Reset
dsPIC33FJ16(GP/MC)101/102
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
LOCK
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= PLL Lock time (1.5 ms nominal) if PLL is enabled.
= Oscillator Start-up Delay (1.1 s max. for FRC, 70 s max. for LPRC). Crystal oscillator start-up
Start-up Delay
Oscillator
T
T
T
T
T
T
T
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
—
—
OST
(1)
(1)
(1)
(1)
(1)
(1)
(1)
= 32 ms for a 32 kHz crystal.
Oscillator Start-up
T
T
T
T
and
Timer
OST
OST
OST
OST
—
—
—
—
—
(2)
(2)
(2)
(2)
A Warm Reset is the result of all other Reset sources,
including the RESET instruction. On Warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selec-
tion (COSC<2:0>) bits in the Oscillator Control
(OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is shown in
PLL Lock Time
T
T
T
LOCK
LOCK
LOCK
—
—
—
—
—
—
(3)
(3)
(3)
 2011-2012 Microchip Technology Inc.
T
OSCD
T
Figure
T
T
T
OSCD
(1)
OSCD
OSCD
OSCD
OST
Total Delay
+ T
T
T
(1)
T
OSCD
LOCK
= 102.4 s for a
(1)
(1)
(1)
6-2.
OST
OSCD
—
+ T
+ T
+ T
+ T
(2)
(3)
(1)
LOCK
OST
OST
OST
+ T
(2)
(2)
(2)
LOCK
(3)
(3)