dsPIC33FJ32GP102-I/SO Microchip Technology, dsPIC33FJ32GP102-I/SO Datasheet - Page 79

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dsPIC33FJ32GP102-I/SO

Manufacturer Part Number
dsPIC33FJ32GP102-I/SO
Description
Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
Manufacturer
Microchip Technology
Type
dsPIC33FJ32(GP/MC)101/102/104r
Datasheet

Specifications of dsPIC33FJ32GP102-I/SO

Rohs
yes
Core
dsPIC33F
Data Bus Width
16 bit
Program Memory Size
32 KB
Data Ram Size
2 KB
Maximum Clock Frequency
7.37 MHz, 32 kHz
Number Of Programmable I/os
21
Number Of Timers
5 x 16-bit, 2 x 32-bit
Device Million Instructions Per Second
16 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Package / Case
QFN-28
Mounting Style
SMD/SMT
Family / Core
dsPIC33FJ32(GP/MC)101/102/104
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
Yes
Product
DSPs
Program Memory Type
Flash
Supply Current
10 mA
4.6
The
dsPIC33FJ32(GP/MC)101/102/104 architecture uses
a 24-bit-wide program space and a 16-bit-wide data
space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
Aside from normal execution, the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
architecture provides two methods by which program
space can be accessed during operation:
• Using table instructions to access individual
• Remapping a portion of the program space into
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for lookups
from a large table of static data. The application can
only access the lsw of the program word.
TABLE 4-42:
 2011-2012 Microchip Technology Inc.
Instruction Access
(Code Execution)
TBLRD/TBLWT
(Byte/Word Read/Write)
Program Space Visibility
(Block Remap/Read)
Note 1:
bytes, or words, anywhere in the program space
the data space (Program Space Visibility)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Access Type
Interfacing Program and Data
Memory Spaces
dsPIC33FJ16(GP/MC)101/102
Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
PROGRAM SPACE ADDRESS CONSTRUCTION
User
User
Configuration
User
Access
Space
and
<23>
0
0
0
TBLPAG<7:0>
TBLPAG<7:0>
0xxx xxxx
1xxx xxxx
0xx
4.6.1
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the MSb of TBLPAG is used to determine if
the
(TBLPAG<7> = 0)
(TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the MSb
of the EA is ‘1’, PSVPAG is concatenated with the lower
15 bits of the EA to form a 23-bit program space
address. Unlike table operations, this limits remapping
operations strictly to the user memory area.
Table 4-42
created for table operations and remapping accesses
from the data EA.
<22:16>
xxxx xxxx
PSVPAG<7:0>
xxxx
operation
Program Space Address
and
ADDRESSING PROGRAM SPACE
xxxx
PC<22:1>
Figure 4-9
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
<15>
occurs
or
xxxx
the
show how the program EA is
xxx xxxx xxxx xxxx
Data EA<15:0>
Data EA<15:0>
in
xxxx xxx0
configuration
<14:1>
Data EA<14:0>
the
DS70652E-page 79
user
memory
memory
(1)
<0>
0

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