IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 11

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.3.2 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length,
read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power-Down, which include
vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting
low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to the
following figure.
2.3.2.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3
as shown in Figure 2.3.2. The ordering of accesses within a burst is determined by the burst length, burst type, and the
starting column address as shown in Table below. The burst length is defined by bits A0-A1. Burst length options include
fixed BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or
Write command via A12/BC#.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
1. A14 and A13 must be programmed to 0 during MRS.
2.
3. The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
BA1 BA0
0
0
1
1
WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The
programmed WR value is used with tRP to determine tDAL.
frequency
WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer:
BA2 BA1 BA0
A12
0
1
0
1
0
1
0
A8
0
0
1
Slow exit (DLL off)
Fast exit (DLL on)
DLL Control for
MR Select
Precharge PD
MR0
MR1
MR2
MR3
0
DLL Reset
Yes
No
A14-A13
0*
1
Write recovery for autoprecharge
PPD
A12
A11
0
0
0
0
1
1
1
1
A11
A10
A7
0
1
0
0
1
1
0
0
1
1
Figure 2.3.2 — MR0 Definition
A10
WR
A9
0
1
0
1
0
1
0
1
Nomal
mode
Test
A9
WR(cycles)
DLL TM
A8
Reserved
10
12
14
5
6
7
8
*2
*2
*2
*2
*2
*2
*2
A7
A3
0
1
Read Burst Type
Nibble Sequential
A6
CAS Latency
Interleave
A5
A4
A6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RBT
A3
A5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A2
CL
A1
A4
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
A0
A2
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BL
A0
BC4 or 8 (on the fly)
CAS Latency
Address Field
Mode Register 0
BC4 (Fixed)
8 (Fixed)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BL
10
11
12
13
14
5
6
7
8
9
11