IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 8

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

VDD,VDDQ
CMMAND
IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
2.2.2 Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
RESET#
CK,CK#
Note1. From time point “Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET needs
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
CKE
ODT
RTT
BA
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 SDRAM is now ready for normal operation.
to be maintained for minimum 100 ns. CKE is pulled “LOW” before RESET being de-asserted (min. time 10 ns).
provide "High" to A8 and "Low" to BA0-2).
Ta
T=200µS
Tmin=10nS
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Figure2.1.1 Reset and Initialization Sequence at Power-on Ramping
T=500µS
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Td
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Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
tXPR
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Time
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ZQCL
tDLLK
Ti
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CARE
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tIS
Valid
Valid
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Valid
Tk
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