IS46TR16128A-15HBLA2 ISSI, IS46TR16128A-15HBLA2 Datasheet - Page 65

• Manufacturer Part Number: IS46TR16128A-15HBLA2
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA2

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
9.2.2 Timing Parameter by Speed Bin (DDR3-1866)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Write leveling setup time from rising CK, CK#
Cumulative error across n = 13, 14 . . . 49, 50
Data setup time to DQS, DQS# referenced to
Data setup time to DQS, DQS# referenced to
DQS/DQS# delay after write leveling mode is
Clock Period Jitter during DLL locking period
Minimum Clock Cycle Time (DLL off mode)
DQS# crossing to rising CK, CK# crossing
Write leveling hold time from rising DQS,
DQS, DQS# to DQ skew, per group, per
DQ high impedance time from CK, CK#
First DQS/DQS# rising edge after write
crossing to rising DQS, DQS# crossing
Cycle to Cycle Period Jitter during DLL
DQ low-impedance time from CK, CK#
DQ output hold time from DQS, DQS#
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Absolute clock HIGH pulse width
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Absolute clock LOW pulse width
leveling mode is programmed
Cycle to Cycle Period Jitter
Write leveling output delay
Write leveling output error
Average high pulse width
Average low pulse width
Write Leveling Timings
Absolute Clock Period
Average Clock Period
Vih(ac) / Vil(ac) levels
Vih(ac) / Vil(ac) levels
Clock Period Jitter
Duty Cycle Jitter
locking period
Clock Timing
programmed
Data Timing
Parameter
Parameter
access
cycles
tCK(DLL_OFF)
tERR(10per)
tERR(11per)
tERR(12per)
tWLDQSEN
JIT(per, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(nper)
JIT(cc, lck)
tDS(base)
tDS(base)
tJIT(duty)
tWLMRD
tCH(avg)
tCH(abs)
tCK(avg)
tCL(avg)
tCK(abs)
tCL(abs)
tHZ(DQ)
tLZ(DQ)
JIT(per)
Symbol
Symbol
tJIT(cc)
tWLOE
tDQSQ
AC175
AC150
tWLS
tWLH
tWLO
tQH
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
DDR3/DDR3L-1333
DDR3/DDR3L-1866
See table for Data
Refer to Standard Speed Bins
Min.
Min.
0.47
0.47
0.43
0.43
-105
-117
-126
-133
-139
-145
-150
-154
-158
-161
0.38
-390
Setup and Hold
195
195
120
100
-60
-50
-88
40
25
0
0
8
-
-
-
Max.: tCK(avg)max + tJIT(per)max
tERR(nper)max = (1 + 0.68ln(n)) *
Min.: tCK(avg)min + tJIT(per)min
Max.
Max.
0.53
0.53
120
100
105
117
126
133
139
145
150
154
158
161
195
195
60
50
88
85
tJIT(per)max
9
2
-
-
-
-
-
-
-
-
-
DDR3/DDR3L-1600
DDR3/DDR3L-1866
Min.
Min.
165
165
40
25
0
0
-
-
-
-
Max.
Max.
7.5
2
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
Units
nCK
nCK
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
65
13,14,f
13,14,f
Notes
Notes
13,g
d,17
d,17
25
26
13
3
6
f