SSTUB32866EC/G,518 NXP Semiconductors, SSTUB32866EC/G,518 Datasheet - Page 10

• Manufacturer Part Number: SSTUB32866EC/G,518
• Description: IC REG BUFFER 25BIT 96-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32866EC/G,518

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Package / Case: 96-LFBGA
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Logic Family: SSTU
• Number Of Circuits: 1
• Maximum Clock Frequency: 450 MHz
• Propagation Delay Time: 1.5 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage (max): 2 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3543-2; 935281279518; SSTUB32866EC/G-T

NXP Semiconductors
Table 5.
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
[1]
[2]
[3]
[4]
8. Limiting values
Table 6.
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
[2]
SSTUB32866_4
Product data sheet
Symbol
V
V
V
I
I
I
I
T
V
IK
OK
O
CCC
RESET
stg
DD
I
O
ESD
H
H
H
H
H
H
H
H
H
H
PPO
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed.
This value is limited to 2.5 V maximum.
L
0
is the previous state of output PPO; QERR
Parity and standby function table
Limiting values
X or floating X or floating X or floating X or floating
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
continuous current through
each V
storage temperature
electrostatic discharge
voltage
DCS
H
H
H
H
H
X
L
L
L
L
DD
or GND pin
CSR
X
X
X
X
H
X
L
L
L
L
Conditions
receiver
driver
V
V
continuous; 0 V < V
Human Body Model (HBM); 1.5 kΩ; 100 pF
Machine Model (MM); 0 Ω; 200 pF
All information provided in this document is subject to legal disclaimers.
I
O
L or H
< 0 V or V
CK
< 0 V or V
↑
↑
↑
↑
↑
↑
↑
↑
↑
Inputs
0
is the previous state of output QERR.
Rev. 04 — 15 April 2010
I
O
> V
1.8 V DDR2-800 configurable registered buffer with parity
> V
L or H
DD
CK
↓
↓
↓
↓
↓
↓
↓
↓
↓
DD
O
↑
< V
= LOW to HIGH transition;
DD
∑ of inputs = H
X or floating
(D1 to D25)
even
even
even
even
odd
odd
odd
odd
X
X
X or floating
PAR_IN
↓
H
H
H
H
X
X
Min
−0.5
−0.5
−0.5
-
-
-
-
−65
2
200
L
L
L
L
SSTUB32866
= HIGH to LOW transition.
[2]
[1]
[1]
PPO
PPO
PPO
Max
+2.5
+2.5
V
−50
±50
±50
±100
+150
-
-
© NXP B.V. 2010. All rights reserved.
DD
H
H
H
H
L
L
L
L
L
Outputs
[3]
[2]
+ 0.5
0
0
[2]
QERR
QERR
QERR
[1]
10 of 30
H
H
H
H
H
L
L
L
L
Unit
V
V
V
mA
mA
mA
mA
°C
kV
V
[4]
0
0