SSTUH32864EC/G,518 NXP Semiconductors, SSTUH32864EC/G,518 Datasheet

SSTUH32864EC/G,518

Manufacturer Part Number

SSTUH32864EC/G,518

Description

IC BUFFER 1.8V 1/14BIT SOT536-1

Manufacturer

NXP Semiconductors

Datasheet

1.SSTUH32864ECG518.pdf (20 pages)

Specifications of SSTUH32864EC/G,518

Logic Type

1:2 Configurable Registered Buffer

Supply Voltage

1.7 V ~ 1.9 V

Number Of Bits

25, 14

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

96-LFBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

935277952518
SSTUH32864EC/G-T
SSTUH32864EC/G-T

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1. General description

The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer designed

for 1.7 V to 1.9 V V

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTUH32864 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout conﬁguration of the 1 : 2 pinout from A conﬁguration

(when LOW) to B conﬁguration (when HIGH). The C1 input controls the pinout

conﬁguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and un-driven (ﬂoating) data, clock and

reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all

registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs

must always be held at a valid logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUH32864 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from

changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is

LOW, the Qn outputs will function normally. The RESET input has priority over the DCS

and CSR control and will force the outputs LOW. If the DCS-control functionality is not

desired, then the CSR input can be hardwired to ground, in which case the setup time

requirement for DCS would be the same as for the other Dn data inputs.

The SSTUH32864 is available in a 96-ball, low proﬁle ﬁne-pitch ball grid array (LFBGA96)

package.

SSTUH32864

1.8 V high output drive conﬁgurable registered buffer for

DDR2 RDIMM applications

Rev. 01 — 22 April 2005

operation.

Product data sheet

Related parts for SSTUH32864EC/G,518

SSTUH32864EC/G,518 Summary of contents

Page 1

SSTUH32864 1.8 V high output drive conﬁgurable registered buffer for DDR2 RDIMM applications Rev. 01 — 22 April 2005 1. General description The SSTUH32864 is a 25-bit 14-bit conﬁgurable registered buffer designed for ...

Page 2

Philips Semiconductors The SSTUH32864 is identical to SSTU32864 in function and performance, with higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while maintaining speed and signal integrity. 2. Features Conﬁgurable register supporting DDR2 Registered DIMM applications ...

Page 3

Philips Semiconductors 4. Functional diagram (1) Disabled conﬁguration. Fig 1. Functional diagram of SSTUH32864 mode (positive logic) 9397 750 14137 Product data sheet 1.8 V high output drive DDR registered buffer RESET CK ...

Page 4

Philips Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin conﬁguration for LFBGA96 Fig 3. Ball mapping register ( 0); top view 9397 750 14137 Product data sheet 1.8 V high output drive ...

Page 5

Philips Semiconductors Fig 4. Ball mapping register A ( 1); top view Fig 5. Ball mapping register B ( 1); top view 9397 750 14137 Product ...

Page 6

Philips Semiconductors 5.2 Pin description Table 2: Pin description Symbol Pin GND B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3 A4, C3, C4, E3, DD E4, G3, G4, J3, J4, L3, L4, N3, ...

Page 7

Philips Semiconductors 6. Functional description 6.1 Function table Table LOW voltage level HIGH voltage level don’t care; = HIGH-to-LOW transition RESET ...

Page 8

Philips Semiconductors 7. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V receiver input voltage I V driver output voltage O I input clamp current IK ...

Page 9

Philips Semiconductors 8. Recommended operating conditions Table 5: Operating conditions Symbol Parameter V supply voltage DD V reference voltage ref V termination voltage TT V input voltage HIGH-level input voltage data inputs (Dn), IH(AC LOW-level ...

Page 10

Philips Semiconductors 9. Characteristics Table 6: Characteristics Recommended operating conditions; T unless otherwise speciﬁed Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I static standby current DD static operating current I dynamic ...

Page 11

Philips Semiconductors Table 7: Timing requirements Recommended operating conditions; T See Figure 6 through Figure 11. Symbol Parameter f clock frequency clock t pulse duration, CK, CK HIGH or W LOW t differential inputs active time ACT t differential inputs ...

Page 12

Philips Semiconductors 10. Test information 10.1 Test circuit All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time with one transition per measurement. CK inputs (1) C ...

Page 13

Philips Semiconductors Fig 9. Voltage waveforms; setup and hold times Fig 10. Voltage waveforms; propagation delay times (clock to output) Fig 11. Voltage waveforms; propagation delay times (reset to output) 9397 750 14137 Product data sheet ...

Page 14

Philips Semiconductors 10.2 Output slew rate measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 12. Load circuit, HIGH-to-LOW slew measurement Fig 13. Voltage waveforms, ...

Page 15

Philips Semiconductors 11. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ...

Page 16

Philips Semiconductors 12. Soldering 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...

Page 17

Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...

Page 18

Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...

Page 19

Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualiﬁcation III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 20

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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