IDT74SSTUBH32865ABKG8 IDT, Integrated Device Technology Inc, IDT74SSTUBH32865ABKG8 Datasheet
IDT74SSTUBH32865ABKG8
Specifications of IDT74SSTUBH32865ABKG8
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IDT74SSTUBH32865ABKG8 Summary of contents
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REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V V operation. DD All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Block Diagram V REF PARIN D0 D21 DCS0 CSGateEN DCS1 DCKE0, DCKE1 DODT0, DODT1 RESET CLK CLK 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 (CS ACTIVE ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Pin Configuration 160-Ball BGA TOP VIEW 28-BIT 1:2 ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Ball Assignment Signal Group Signal Name DCKE0, DCKE1, Ungated Inputs DODT0, DODT1 Chip Select Gated Inputs Chip Select Inputs DCS0, DCS1 Re-Driven Parity Input Parity Error Program Inputs Clock Inputs Miscellaneous Inputs 28-BIT ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Function Table RESET DCS0 DCS1 ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Parity and Standby Function Table RESET DCS0 DCS1 ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Operating Characteristics The RESET and CSGateEN inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Timing Requirements Over Recommended Operating Free-Air Temperature Range Symbol Parameter f Clock Frequency CLOCK t Pulse Duration; CLK, CLK HIGH or LOW W t Differential Inputs Active Time ACT t Differential Inputs Inactive ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range Parameter dV/dt_r dV/dt_f 1 dV/dt_Δ 1 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 28-BIT 1:2 REGISTERED BUFFER ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Parity Logic Diagram PARIN CLOCK Register Timing CLK CLK PARIN PTYERR 28-BIT 1:2 REGISTERED BUFFER FOR ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT T = 50Ω L CLK Out CLK Inputs CLK Test Point R 100Ω Test Point Simulation Load Circuit LVCMOS RESET Input t ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT Out Load Circuit: High-to-Low Slew-Rate Adjustment Output 80% 20% dv_f dt_f Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Package Outline and Package Dimensions - BGA Package dimensions are kept current with JEDEC Publication No. 95 ROW A, COLUMN ALL DIMENSIONS IN MILLIMETERS Min/Max 13.00 Bsc ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Ordering Information IDT XX SSTUBH XX Family Temp. Range 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 XXX XX X Device Type Package Shipping Carrier 8 BKG 865A COMMERCIAL TEMPERATURE GRADE Tape ...
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IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...