IDT74SSTUBH32865ABKG8 IDT, Integrated Device Technology Inc, IDT74SSTUBH32865ABKG8 Datasheet - Page 4

• Manufacturer Part Number: IDT74SSTUBH32865ABKG8
• Description: IC BUFFER 28BIT 1:2 REG 160-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74SSTUBH32865ABKG8

• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74SSTUBH32865ABKG8

Ball Assignment
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
Chip Select Gated
Chip Select Inputs
Signal Group
Program Inputs
Ungated Inputs
Miscellaneous
Clock Inputs
Parity Input
Parity Error
Re-Driven
Inputs
Inputs
DCKE0, DCKE1,
DODT0, DODT1
Signal Name
DCS0, DCS1
Q0A...Q21A,
Q0B...Q21B,
QCKEnA,B,
QODTnA,B
CSGateEN
MCL, MCH
D0 ... D21
CLK, CLK
QCSnA,B
PTYERR
RESET
PARIN
V
REF
1.8V LVCMOS
1.8V LVCMOS
0.9V nominal
Open Drain
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
Type
4
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is
LOW.
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one
will be low when a valid address/command is present.
The register can be programmed to re-drive all
D-inputs only (CSGateEN high) when at least one
Chip Select input is LOW.
Outputs of the register, valid after the specified clock
count outputs and immediately following a rising edge
of the clock.
Input parity is received on pin PARIN and should
maintain odd parity across the D0...D21 inputs, at the
rising edge of the clock.
When LOW, this output indicates that a parity error
was output identified associated with the address
and/or command inputs. PTYERR will be active for
two clock cycles, and delayed by an additional clock
cycle for compatibility with final parity out timing on
the industry-standard DDR-II register with parity (in
JEDEC definition).
Chip Select Gate Enable. When HIGH, the D0..D21
inputs will be latched only when at least one Chip
Select input is LOW during the rising edge of the
clock. When LOW, the D0...D21 inputs will be latched
and redriven on every rising edge of the clock.
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CLK).
Must be connected to a logic LOW or HIGH.
Asynchronous reset input. When LOW, it causes a
reset of the internal latches, thereby forcing the
outputs LOW. RESET also resets the PTYERR
signal.
Input reference voltage for the SSTL_18 inputs. Two
pins (internally tied together) are used for increased
reliability.
COMMERCIAL TEMPERATURE GRADE
Description
IDT74SSTUBH32865A
7103/10