LCMXO640E-5FN256C Lattice, LCMXO640E-5FN256C Datasheet - Page 9

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LCMXO640E-5FN256C

Manufacturer Part Number
LCMXO640E-5FN256C
Description
CPLD - Complex Programmable Logic Devices Use LCMXO640E-5FTN25
Manufacturer
Lattice
Datasheet

Specifications of LCMXO640E-5FN256C

Rohs
yes
Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
600 MHz
Delay Time
3.5 ns
Number Of Programmable I/os
159
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
14 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V
Lattice Semiconductor
Figure 2-6. Distributed Memory Primitives
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Routing
There are many resources provided in the MachXO devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2
(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connec-
tions in the horizontal and vertical directions.
MUX 16x1 x 1
MUX 2x1 x 8
MUX 4x1 x 4
MUX 8x1 x 2
LUT 6x 2 or
LUT 4x8 or
LUT 5x4 or
LUT 7x1 or
WRE
Logic
AD0
AD1
AD2
AD3
AD0
AD1
AD2
AD3
DI0
DI1
CK
ROM16x1
SPR16x2
2-bit Counter x 4
2-bit Comp x 4
2-bit Add x 4
2-bit Sub x 4
Ripple
DO0
DO0
DO1
2-6
DPR16x2 x 2
DPR16x4 x 1
SPR16x2 x 4
SPR16x4 x 2
SPR16x8 x 1
WAD0
WAD1
WAD2
WAD3
WCK
WRE
RAM
DI0
DI1
DPR16x2
MachXO Family Data Sheet
ROM16x1 x 8
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
ROM
RAD0
RAD1
RAD2
RAD3
RDO0
RDO1
WDO0
WDO1
Architecture

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