MAX1301BEUP+CAL Maxim Integrated, MAX1301BEUP+CAL Datasheet - Page 19

• Manufacturer Part Number: MAX1301BEUP+CAL
• Description: Analog to Digital Converters - ADC Intel R2 Customer special for MAX1301BEUP+
• Manufacturer: Maxim Integrated

Specifications of MAX1301BEUP+CAL

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 130 KSPs
• Input Type: Single-Ended/Differential
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 879 mW
• Number Of Converters: 1

Figure 7. Single-Ended Input Voltage Ranges
The MAX1300/MAX1301 feature a serial interface that is
compatible with SPI/QSPI and MICROWIRE devices.
DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirec-
tional communication between the MAX1300/MAX1301
and the master at SCLK rates up to 10MHz (internal
clock mode, mode 2), 3.67MHz (external clock mode,
mode 0), or 4.39MHz (external acquisition mode, mode
1). The master, typically a microcontroller, should use
the CPOL = 0, CPHA = 0, SPI transfer format, as shown
in the timing diagrams of Figures 2, 3, and 4.
The digital interface is used to:
• Select single-ended or true-differential input channel
• Select the unipolar or bipolar input range
• Select the mode of operation:
• Initiate conversions and read results
8- and 4-Channel, ±3 x V
configurations
(+3 x V
(-3 x V
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
+3 x V
-3 x V
REF
REF
REF
REF
)/2
)/2
0
EACH INPUT IS FAULT TOLERANT TO ±16.5V.
V
REF
= 4.096V.
______________________________________________________________________________________
INPUT RANGE SELECTION BITS, R[2:0]
Digital Interface
CS enables communication with the MAX1300/MAX1301.
When CS is low, data is clocked into the device from DIN
on the rising edge of SCLK and data is clocked out of
DOUT on the falling edge of SCLK. When CS is high,
activity on SCLK and DIN is ignored and DOUT is high
impedance allowing DOUT to be shared with other
peripherals. SSTRB is never high impedance and there-
fore cannot be shared with other peripherals.
As shown in Figures 3 and 4, the SSTRB transitions high
to indicate that the ADC has completed a conversion
and results are ready to be read by the master. SSTRB
remains low in the external clock mode (Figure 2) and
consequently may be left unconnected. SSTRB is driven
high or low regardless of the state of CS, therefore
SSTRB cannot be shared with other peripherals.
Figure 8. Differential Input Voltage Ranges
REF
+6 x V
+3 x V
-3 x V
-6 x V
REF
REF
REF
REF
0
EACH INPUT IS FAULT TOLERANT TO ±16.5V.
V
Serial 16-Bit ADCs
Multirange Inputs,
REF
= 4.096V.
INPUT RANGE SELECTION BITS, R[2:0]
Serial Strobe Output (SSTRB)
Chip Select (CS)
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