MAX1301BEUP+CAL Maxim Integrated, MAX1301BEUP+CAL Datasheet - Page 23

• Manufacturer Part Number: MAX1301BEUP+CAL
• Description: Analog to Digital Converters - ADC Intel R2 Customer special for MAX1301BEUP+
• Manufacturer: Maxim Integrated

Specifications of MAX1301BEUP+CAL

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 130 KSPs
• Input Type: Single-Ended/Differential
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 879 mW
• Number Of Converters: 1

Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
Figure 16. DOUT and SSTRB Timing
Table 7. Mode-Control Byte
BIT NUMBER
8- and 4-Channel, ±3 x V
DOUT
SCLK
DIN
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
CS
• The internal clock controls the sampling instant
• User supplies one byte of SCLK, then drives CS
7
6
5
4
3
2
1
0
IMPEDANCE
high to relieve processor load while the ADC
converts
t
t
DV
CSS
HIGH
t
DS
SSTRB
DOUT
SCLK
CS
START
t
SSCS
1
BIT NAME
______________________________________________________________________________________
t
START
CL
IMPEDANCE
SEL2
M2
M1
M0
HIGH
t
1
0
0
0
CSS
ANALOG INPUT CONFIGURATION BYTE
SEL1
t
DO
SEL0
Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
Bit 3 must be a logic 1 for the mode-control byte.
Bit 2 must be a logic 0 for the mode-control byte.
Bit 1 must be a logic 0 for the mode-control byte.
Bit 0 must be a logic 0 for the mode-control byte.
MSB
t
CP
DIF/SGL
t
CH
R2
R1
t
CSH
R0
t
t
8
DH
TR
IMPEDANCE
HIGH
The MAX1300/MAX1301’s fastest maximum throughput
rate is achieved operating in external clock mode.
SCLK controls both the acquisition and conversion of
the analog signal, facilitating precise control over when
the analog signal is captured. The analog input sam-
pling instant is at the falling edge of the 14th SCLK
(Figure 2).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1300/
MAX1301 will always be used in the external clock mode.
REF
t
CSPW
START
• After SSTRB transitions high, the user supplies
1
DESCRIPTION
two bytes of SCLK and reads data at DOUT
M2
Serial 16-Bit ADCs
Multirange Inputs,
M1
MODE CONTROL BYTE
M0
External Clock Mode (Mode 0)
1
0
0
0
8
IMPEDANCE
HIGH
23