C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 326

• Manufacturer Part Number: C8051F964-A-GQ
• Description: 8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F964-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
SFR Definition 25.6. PC0DCL: PC0 Debounce Configuration Low
SFR Address = 0xF9; SFR Page = 0x2
326
Name
Reset
7:0
Bit
Type
Bit
PC0DCL[7:0]
7
0
Name
6
0
Pulse Counter Debounce Low
Number of cumulative good samples seen by the integrator before recogniz-
ing the input as low. Setting PC0DCL to 0x00 will disable integrators on both
PC0 and PC1. The actual value used is PC0DCL plus one. Sampling a low
decrements while sampling a high increments the count. Switch bounce
produces a random looking signal. The worst case would be to bounce high
at each sample point and not start decrementing the integrator until the
switch bounce settled. Therefore, minimum pulse width should account for
twice the debounce time. For example, using a sample rate of 1 ms and a
PC0DCL value of 0x09 will look for 10 cumulative lows before recognizing
the input as low (1 ms x 10 = 10 ms). The minimum pulse width should be
20 ms or greater for this example. If PC0DCL has a value of 0x03 and the
sample rate is 500 µs, the integrator would need to see 4 cumulative lows
before recognizing the low (500 µs x 4 = 2 ms). The minimum pulse width
should be 4 ms for this example.
5
0
Rev. 0.5
4
0
PC0DCL[7:0]
R/W
3
0
Function
2
1
1
0
0
0