LPC11E14FBD64/401, NXP Semiconductors, LPC11E14FBD64/401, Datasheet - Page 14

• Manufacturer Part Number: LPC11E14FBD64/401,
• Description: ARM Microcontrollers - MCU 32kB 4kB EE 10kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11E14FBD64/401,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11E1x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 160

NXP Semiconductors
7. Functional description
LPC11E1X
Product data sheet
7.1 On-chip flash programming memory
7.2 EEPROM
7.3 SRAM
7.4 On-chip ROM
7.5 Memory map
The LPC11E1x contain 24 kB or 32 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
The LPC11E1x contain 500 Byte, 1 kB, 2 kB, or 4 kB of on-chip byte-erasable and
byte-programmable EEPROM data memory. The EEPROM can be programmed using
In-Application Programming (IAP) via the on-chip boot loader software.
The LPC11E1x contain a total of 4 kB, 6 kB, 8 kB, or 10 kB on-chip static RAM memory.
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
The LPC11E1x incorporates several distinct memory regions, shown in the following
figures.
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This addressing scheme allows
simplifying the address decoding for each peripheral.
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•
•
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In-System Programming (ISP) and In-Application Programming (IAP) support for flash
IAP support for EEPROM
Power profiles for configuring power consumption and PLL settings
32-bit integer division routines
Figure 5
All information provided in this document is subject to legal disclaimers.
shows the overall map of the entire address space from the user
Rev. 1 — 20 February 2012
32-bit ARM Cortex-M0 microcontroller
LPC11E1x
© NXP B.V. 2012. All rights reserved.
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