LPC11E14FBD64/401, NXP Semiconductors, LPC11E14FBD64/401, Datasheet - Page 8

• Manufacturer Part Number: LPC11E14FBD64/401,
• Description: ARM Microcontrollers - MCU 32kB 4kB EE 10kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11E14FBD64/401,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11E1x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 160

NXP Semiconductors
Table 3.
LPC11E1X
Product data sheet
Symbol
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/SCK0
PIO0_7/CTS
Pin description
6.2 Pin description
Table 3
port number. The default function after reset is listed first. All port pins have internal
pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
15
2
3
8
9
10
11
16
shows all pins and their assigned digital or analog functions in order of the GPIO
3
4
10
14
15
16
22
23
4
5
13
19
20
21
29
30
All information provided in this document is subject to legal disclaimers.
[2]
[3]
[3]
[3]
[4]
[4]
[3]
[5]
Reset
state
[1]
I; PU
-
I; PU
-
-
I; PU
-
-
I; PU
I; IA
-
I; IA
-
I; PU
-
I; PU
-
Rev. 1 — 20 February 2012
Type Description
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address
0. This pin also serves as the debug select input. LOW
level selects the JTAG boundary scan. HIGH level selects
the ARM SWD debug mode.
PIO0_0 — General purpose digital input/output pin.
PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command
handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave select for SSP0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin.
PIO0_4 — General purpose digital input/output pin
(open-drain).
SCL — I
High-current sink only if I
the I/O configuration register.
PIO0_5 — General purpose digital input/output pin
(open-drain).
SDA — I
High-current sink only if I
the I/O configuration register.
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SSP0.
PIO0_7 — General purpose digital input/output pin
(high-current output driver).
CTS — Clear To Send input for USART.
2
2
C-bus clock input/output (open-drain).
C-bus data input/output (open-drain).
32-bit ARM Cortex-M0 microcontroller
2
2
C Fast-mode Plus is selected in
C Fast-mode Plus is selected in
LPC11E1x
© NXP B.V. 2012. All rights reserved.
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