MPC8308VMAGDA Freescale Semiconductor, MPC8308VMAGDA Datasheet - Page 5
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MPC8308VMAGDA
Manufacturer Part Number
MPC8308VMAGDA
Description
Microprocessors - MPU E300 MP PbFr 400
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8308VMAGDA.pdf
(83 pages)
Specifications of MPC8308VMAGDA
Rohs
yes
Processor Series
MPC8308
Core
e300
Maximum Clock Frequency
400 MHz
Interface Type
I2C, JTAG, UART
Operating Supply Voltage
0.95 V to 1.05 V
Maximum Operating Temperature
0 C to + 105 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8308VMAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
This figure shows the undershoot and overshoot voltages at the interfaces of the device.
2.1.3
This table provides information on the characteristics of the output driver strengths.
2.1.4
It is required to apply the core supply voltage (V
NV
to 90% of its nominal value before the I/O supplies reach 0.7 V; see
If this recommendation is not observed and I/O voltages are supplied before the core voltage, there might
be a period of time that all input and output pins are actively driven and cause contention and excessive
current. To overcome side effects of this condition, the application environment may require tuning of
external pull-up or pull-down resistors on particular signals to lesser values.
Freescale Semiconductor
DD
1
Local bus interface utilities signals
DDR2 signals
DUART, system control, I
eTSEC signals
) and assert PORESET before the power supplies fully ramp up. The core voltage supply must rise
Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR).
For more information, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.
Output Driver Characteristics
Power Sequencing
V
V
Note:
IH
1. t
IL
1
interface
G/L/NV
G/L/NV
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD
VSS – 0.3 V
VSS – 0.7 V
refers to the clock period associated with the bus clock interface.
G/L/NV
DD
DD
Driver Type
2
C, JTAG, eSDHC, GPIO,SPI, USB
+ 20%
+ 5%
VSS
DD
Table 3. Output Drive Capability
DD
Not to Exceed 10%
) before the I/O supply voltages (GV
of t
interface
Output Impedance ()
1
42
18
42
42
Figure
3.
LV
Supply Voltage
NV
GV
NV
DD
Electrical Characteristics
DD
DD
DD
= 2.5/3.3 V
DD
= 3.3 V
= 3.3 V
= 1.8 V
, LV
DD
, and
5