MPC8308VMAGDA Freescale Semiconductor, MPC8308VMAGDA Datasheet - Page 73

• Manufacturer Part Number: MPC8308VMAGDA
• Description: Microprocessors - MPU E300 MP PbFr 400
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGDA

• Rohs: yes
• Processor Series: MPC8308
• Core: e300
• Maximum Clock Frequency: 400 MHz
• Interface Type: I2C, JTAG, UART
• Operating Supply Voltage: 0.95 V to 1.05 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-473

This table provides the operating frequencies for the device under recommended operating conditions
(Table
21.2
The system PLL is controlled by the RCWL[SPMF] parameter. This table shows the multiplication factor
encodings for the system PLL.
As described in
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
coherent system bus clock (csb_clk). This table shows the expected frequency values for the CSB
frequency for select csb_clk to SYS_CLK_IN ratios.
Freescale Semiconductor
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
DDR2 memory bus frequency (MCK)
Local bus frequency (LCLK0)
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on LCCR[CLKDIV]) which is in turn, 1x or 2x
MCK, LCLK0, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
the csb_clk frequency (depending on RCWL[LBCM]).
2).
System PLL Configuration
Section 21, “Clocking,”
csb_clk :Input Clock Ratio
0010
0100
0101
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Characteristic
3
SPMF
Table 55. Operating Frequencies for MPC8308
2
2:1
4:1
5:1
RCWL[SPMF]
1
0110–1111
Table 57. CSB Frequency Options
0000
0001
0010
0011
0100
0101
Table 56. System PLL Ratio
the LBCM, DDRCM, and SPMF parameters in the reset
125
25
csb_clk: SYS_CLK_IN
Input Clock Frequency (MHz)
Reserved
Reserved
Reserved
Maximum Operating Frequency
2 : 1
3 : 1
4 : 1
5 : 1
33.33
133
167
400
133
133
66
66.67
133
MHz
MHz
MHz
MHz
Unit
Clocking
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