74AUP1T57GW,125 NXP Semiconductors, 74AUP1T57GW,125 Datasheet
74AUP1T57GW,125
Specifications of 74AUP1T57GW,125
74AUP1T57GW-G
935280464125
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74AUP1T57GW,125 Summary of contents
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Low-power configurable gate with voltage-level translator Rev. 3 — 21 July 2010 1. General description The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74AUP1T57GW −40 °C to +125 °C 74AUP1T57GM −40 °C to +125 °C 74AUP1T57GF −40 °C to +125 °C 74AUP1T57GN −40 °C to +125 °C 74AUP1T57GS 4. Marking Table 2. Marking ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP1T57 GND 001aah472 Fig 2. Pin configuration SOT363 6.2 Pin description Table 3. Pin description Symbol Pin B 1 GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 74AUP1T57 Product data sheet Low-power configurable gate with voltage-level translator ...
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... NXP Semiconductors 7.1 Logic configurations Table 5. Function selection table Logic function 2-input AND 2-input AND with both inputs inverted 2-input NAND with inverted input 2-input OR with inverted input 2-input NOR 2-input NOR with both inputs inverted 2-input XNOR Inverter Buffer Fig 5. ...
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... NXP Semiconductors Fig 11. Buffer 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 25 °C T amb V positive-going threshold T+ voltage V negative-going threshold T− voltage V hysteresis voltage H V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI additional supply current CC [1] One input at 0 1.1 V, other input at V [2] One input at 0. 1.2 V, other input ...
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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay see propagation delay see °C T amb C power dissipation MHz capacitance V V [1] All typical values are measured at nominal V ...
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... NXP Semiconductors 12. Waveforms input Measurement points are given in V and V are typical output voltage drop that occur with the output load Fig 12. Input A, B and C to output Y propagation delay times Table 10. Measurement points Supply voltage Output 0.5 × 3.6 V 74AUP1T57 ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 13. Test circuit for measuring switching times Table 11. ...
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... NXP Semiconductors 13. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 14. Package outline SOT363 (SC-88) 74AUP1T57 Product data sheet Low-power configurable gate with voltage-level translator ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 16 ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date 74AUP1T57 v.3 20100721 • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP1T57 Product data sheet Low-power configurable gate with voltage-level translator 16 ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms ...