MPC8536BVTATLA Freescale Semiconductor, MPC8536BVTATLA Datasheet - Page 24

• Manufacturer Part Number: MPC8536BVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

Electrical Characteristics
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
The core voltage must always be provided at nominal 1.0 V . (See
processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in
The input voltage threshold scales with respect to the associated I/O supply voltage. OV
CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface uses
differential receivers referenced by the externally supplied MV
SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers cannot be
operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
24
V
IH
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
V
Note:
1. t
2. With the PCI overshoot allowed (as specified above), the device
IL
Figure 7. Overshoot/Undershoot Voltage for GV
B/G/L/OV
For I
For DDR, t
For eTSEC, t
For eLBC, t
For PCI, t
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
CLOCK
B/G/L/OV
2
C and JTAG, t
GND – 0.3 V
GND – 0.7 V
B/G/L/OV
refers to the clock period associated with the respective interface:
DD
CLOCK
DD
CLOCK
CLOCK
+ 20%
CLOCK
+ 5%
GND
DD
references PCI1_CLK or SYSCLK.
references MCLK.
references LCLK.
CLOCK
references EC_GTX_CLK125.
references SYSCLK.
REF
Table 3
n signal (nominally set to GV
Not to Exceed 10%
of t
for actual recommended core voltage). Voltage to the
CLOCK
1
DD
/OV
DD
and LV
DD
/LV
DD
DD
DD
/2) as is appropriate for the
based receivers are simple
Freescale Semiconductor
Table
3.