MPC8536BVTATLA Freescale Semiconductor, MPC8536BVTATLA Datasheet - Page 89

• Manufacturer Part Number: MPC8536BVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

HRESET high to first FRAME assertion
Rise time (20%–80%)
Failing time (20%–80%)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3. All PCI signals are measured from OV
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
5. Input timings are measured at the pin.
6. The timing parameter t
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
9. The reset assertion timing requirement for HRESET is 100 μs.
This figure provides the AC test load for PCI.
This figure shows the PCI input AC timing conditions.
Freescale Semiconductor
for inputs and t
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, t
going to the high (H) state or setup time. Also, t
high (H) relative to the frame signal (F) going to the valid (V) state.
PCI signaling levels.
the component pin is less than or equal to the leakage current specification.
system clock period must be kept within the minimum and maximum defined ranges. For values see
Specifications .
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter
SYS
PCRHFV
Table 68. PCI AC Timing Specifications at 66 MHz (continued)
Output
indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
Figure 55. PCI Input AC Timing Measurement Conditions
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Input
CLK
DD
/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV
Figure 54. PCI AC Test Load
PCRHFV
Z
0
t
PCIVKH
= 50 Ω
symbolizes PCI timing (PC) with respect to the time hard reset (R) went
Symbol
t
t
t
PCRHFV
PCICLK
PCICLK
1
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
R
L
Min
0.6
0.6
10
= 50 Ω
t
PCIXKH
DD
OV
Max
2.1
2.1
—
of the signal in question for 3.3-V
DD
PCIVKH
/2
Electrical Characteristics
Section 22,
symbolizes PCI timing
clocks
Unit
SYS
ns
ns
, reference (K)
“Clocking.”
Notes
—
—
8
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