MPC8536BVTATLA Freescale Semiconductor, MPC8536BVTATLA Datasheet - Page 90

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MPC8536BVTATLA

Manufacturer Part Number
MPC8536BVTATLA
Description
Microprocessors - MPU 8536 NON E
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8536BVTATLA

Product Category
Microprocessors - MPU
Rohs
yes
Processor Series
PowerQUICC III
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
250 MHz
Program Memory Size
32 KB
Data Ram Size
512 KB
Interface Type
I2C, USB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
0 C to + 105 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-783
Electrical Characteristics
This figure shows the PCI output AC timing conditions.
2.20
This chip features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The
SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for SGMII or SATA.
This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes
Reference Clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.
2.20.1
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.
Figure 57
shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each
signal swings between A Volts and B Volts where A > B.
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes
transmitter and receiver operate in a fully symmetrical differential signaling environment.
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a
The Differential Output Voltage (or Swing) of the transmitter, V
The Differential Input Voltage (or Swing) of the receiver, V
The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak
Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to
90
1.
2.
3.
4.
5.
Single-Ended Swing
Differential Output Voltage, V
Differential Input Voltage, V
Differential Peak Voltage, V
Differential Peak-to-Peak, V
shows how the signals are defined. For illustration purposes, only one SerDes lane is used for description. The figure
High-Speed Serial Interfaces
Signal Terms Definition
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
High-Impedance
peak-to-peak swing of A - B Volts. This is also referred as each signal wire’s Single-Ended Swing.
voltages: V
voltages: V
Voltage, V
-(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential
receiver input signal is defined as Differential Peak-to-Peak Voltage, V
2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential
Figure 56. PCI Output AC Timing Measurement Condition
Output Delay
Output
DIFFp
DIFFp-p
ID
DIFFp
CLK
SDn_TX
SDn_RX
OD
(or Differential Input Swing):
(or Differential Output Swing):
= |A - B| Volts.
- V
- V
SDn_TX.
SDn_RX.
The V
ID
The V
, is defined as the difference of the two complimentary input
t
OD
PCKHOZ
, is defined as the difference of the two complimentary output
t
OD
ID
PCKHOV
value can be either positive or negative.
value can be either positive or negative.
DIFFp-p
Freescale Semiconductor
= 2*V
DIFFp
=

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