MPC8536BVTATLA Freescale Semiconductor, MPC8536BVTATLA Datasheet - Page 35

• Manufacturer Part Number: MPC8536BVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

At recommended operating conditions with GV
MDQS epilogue end
Note:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
7. Maximum DDR2 and DDR3 frequency is 667 MHz
Freescale Semiconductor
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
For the ADDR/CMD setup and hold specifications in
Control register is set to adjust the memory clocks by 1/2 applied cycle.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
follows the symbol conventions described in note 1. For example, t
Table 19. DDR SDRAM Output AC Timing Specifications (continued)
<= 667 MHz
<= 667 MHz
DD
of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
DDKLDX
Symbol
t
DDKHME
MCK
symbolizes DDR timing (DD) for the time t
1
memory clock reference (K) goes from the high (H) state until outputs
NOTE
0.9 × t
0.4 × t
(first two letters of functional block)(signal)(state) (reference)(state)
Min
for outputs. Output hold time can be read as DDR timing
MCK
MCK
Table
19, it is assumed that the Clock
0.6 × t
DDKHMH
Max
DDKHMH
MCK
can be modified through control
describes the DDR timing (DD)
MCK
Electrical Characteristics
memory clock reference
DDKHMP
Unit
ns
follows the
Notes
7
6
7
for
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