DAC1008D650HN/C1 NXP Semiconductors, DAC1008D650HN/C1 Datasheet - Page 87

• Manufacturer Part Number: DAC1008D650HN/C1
• Description: Digital to Analog Converters - DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT
• Manufacturer: NXP Semiconductors

Specifications of DAC1008D650HN/C1

• Rohs: yes
• Factory Pack Quantity: 260

NXP Semiconductors
Table 191. LN3_CFG_3 register (address 13h) bit description
Default settings are shown highlighted.
Table 192. LN3_CFG_4 register (address 14h) bit description
Default settings are shown highlighted.
Table 193. LN3_CFG_5 register (address 15h) bit description
Default settings are shown highlighted.
Table 194. LN3_CFG_6 register (address 16h) bit description
Default settings are shown highlighted.
Table 195. LN3_CFG_7 register (address 17h) bit description
Default settings are shown highlighted.
Table 196. LN3_CFG_8 register (address 18h) bit description
Default settings are shown highlighted.
Table 197. LN3_CFG_9 register (address 19h) bit description
Default settings are shown highlighted.
Table 198. LN3_CFG_10 register (address 1Ah) bit description
Default settings are shown highlighted.
DAC1008D650
Product data sheet
Bit
7
4 to 0
Bit
7 to 0
Bit
4 to 0
Bit
7 to 0
Bit
7 to 6
4 to 0
Bit
4 to 0
Bit
4 to 0
Bit
7
4 to 0
Symbol
LN3_SCR
LN3_L[4:0]
Symbol
LN3_F[7:0]
Symbol
LN3_K[4:0]
Symbol
LN3_M[7:0]
Symbol
LN3_CS[1:0]
LN3_N[4:0]
Symbol
LN3_N'[4:0]
Symbol
LN3_S[4:0]
Symbol
LN3_HD
LN3_CF[4:0]
All information provided in this document is subject to legal disclaimers.
Access
R
R
Access
R
Access
R
Access
R
Access
R
R
Access
R
Access
R
Access
R
R
Rev. 3 — 31 January 2012
Value
-
-
Value
Value
-
Value
-
Value
-
-
Value
-
Value
-
Value
-
-
-
2, 4 or 8 interpolating DAC with JESD204A
Description
scrambling on
number of lanes minus 1
Description
Description
number of frames per multiframe minus 1
Description
number of converters per device minus 1
Description
number of control bits
converter resolution minus 1
Description
number of bits per sample minus 1
Description
number of samples per converter per frame cycle
minus 1
Description
high density
number of octets per frame minus 1
number of control words per frame cycle
DAC1008D650
© NXP B.V. 2012. All rights reserved.
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