1893YI-10LF IDT, 1893YI-10LF Datasheet - Page 27

• Manufacturer Part Number: 1893YI-10LF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893YI-10LF

• Rohs: yes
• Part # Aliases: ICS1893YI-10LF

6.2 100M Symbol Interface
ICS1893 Rev C 6/6/00
The 100M Symbol Interface has a primary objective of supporting 100Base-TX repeater applications for
which the repeater requires only recovered parallel data and for which the repeater provides all the
necessary framing and control functions.
When the ICS1893 MAC/Repeater Interface is configured for 100M Symbol operations, the PHY and the
MAC/repeater exchange unframed 5-bit, parallel symbols at a 25-MHz clock rate.
The configuration functions of the ICS1893 determine the operation of its MAC/Repeater Interface. The
configuration functions are controlled by either input pins (in which case, the HW/SW pin is logic zero to
select the hardware mode) or Management Register bits (in which case, the HW/SW pin is logic one to
select the software mode).
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The 100M Symbol Interface bypasses the ICS1893’ s PCS and provides a direct, unscrambled, unframed,
5-bit interface between the MAC/repeater and the PMA sublayer. A benefit of bypassing the PCS is a
reduction in the latency through the PHY. That is, when the ICS1893’ s MAC/Repeater Interface is
configured as a 100M Symbol Interface, the bit delays through the PHY are smaller than the standard MII
Data Interface can allow. The ICS1893 provides this 100M Symbol Interface primarily for Repeater
applications, for which latency is a critical performance parameter.
In addition to the exchange of symbol data, an ICS1893 configured for 100M Symbol mode provides
ISO/IEC-compliant control signals (such as CRS) to the MAC/repeater. The ICS1893’ s CRS signal
provides a fast look-ahead, which can benefit a repeater application.
In the 100M Symbol Interface mode, the ICS1893 continues to assert the CRS signal using its PCS logic.
This action does not affect the bit delay or latency because the PCS CRS logic examines the bits received
from the PMA sublayer serially. In fact, because the PCS CRS does not wait for a nibble or symbol to be
constructed, the PCS CRS is available in advance of the symbol generation. Therefore, by using the PCS
CRS generation logic, the ICS1893 can provide an ‘ early’ indication of a Carrier Detect to the
MAC/repeater.
The 100M Symbol Interface consists of the following fourteen signals:
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When the ICS1893 MAC/Repeater Interface is configured for 100M Symbol operations, its default MII pin
names and their associated functions are redefined. For more information, see
“ MAC/Repeater Interface Pins for 100M Symbol Interface”
In hardware mode, the ICS1893 enables the 100M Symbol Interface when both of the following are true:
In software mode, the ICS1893 enables the 100M Symbol Interface when both the following are true:
SCRS
SD
SRCLK
SRD[4:0]
STCLK
STD[4:0]
– Its MII/SI input pin is sampled as a logic one (that is, the selection is for the Symbol Interface).
– Its 10/100SEL input pin is sampled as a logic one (that is, the selection is for 100M operations).
– Its MII/SI input pin is sampled as a logic one (that is, the selection is for the Symbol Interface).
– Its Control Register Data Rate bit (bit 0.13) is set to logic one (that is, the selection is for selecting
ICS1893 - Release
100M operations)
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
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Chapter 6 Interface Overviews
Section 9.3.4.2,
June, 2000