1893YI-10LFT IDT, 1893YI-10LFT Datasheet
1893YI-10LFT
Specifications of 1893YI-10LFT
Related parts for 1893YI-10LFT
1893YI-10LFT Summary of contents
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Integrated Circuit Systems, Inc. 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base- ...
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ICS1893 Data Sheet - Release Section Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 11 Chapter 2 Conventions and Nomenclature..................................................................................... 13 Chapter 3 ICS1893 Enhanced Features ........................................................................................... 15 Chapter 4 Overview of the ICS1893.................................................................................................. 17 4.1 100Base-TX Operation ...
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ICS1893 - Release Section 7.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................................ 44 7.3.1 PCS Sublayer ........................................................................................................ 44 7.3.2 PMA Sublayer ........................................................................................................ 44 7.3.3 PCS/PMA Transmit Modules ................................................................................. 45 7.3.4 PCS/PMA Receive Modules .................................................................................. 46 7.3.5 PCS Control Signal ...
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ICS1893 Data Sheet - Release Section Chapter 8 Management Register Set ............................................................................................... 59 8.1 Introduction to Management Register Set ............................................................. 60 8.1.1 Management Register Set Outline ......................................................................... 60 8.1.2 Management Register Bit Access .......................................................................... 61 8.1.3 Management Register Bit Default ...
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ICS1893 - Release Section 8.5 Register 3: PHY Identifier Register ........................................................................ 74 8.5.1 OUI bits 19-24 (bits 3.15:10) .................................................................................. 74 8.5.2 Manufacturer's Model Number (bits 3.9:4) ............................................................. 75 8.5.3 Revision Number (bits 3.3:0) ................................................................................. 75 8.6 Register 4: Auto-Negotiation Register ...
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ICS1893 Data Sheet - Release Section 8.11 Register 16: Extended Control Register ................................................................ 88 8.11.1 Command Override Write Enable (bit 16.15) ......................................................... 89 8.11.2 ICS Reserved (bits 16.14:11) ................................................................................. 89 8.11.3 PHY Address (bits 16.10:6) ................................................................................... 89 8.11.4 Stream Cipher ...
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ICS1893 - Release Section 8.14 Register 19: Extended Control Register 2 ........................................................... 100 8.14.1 Node/Repeater Configuration (bit 19.15) ............................................................. 101 8.14.2 Hardware/Software Priority Status (bit 19.14) ...................................................... 101 8.14.3 Remote Fault (bit 19.13) ...................................................................................... 101 8.14.4 ICS Reserved (bits 19.12:8) ...
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ICS1893 Data Sheet - Release Section 10.5.10 10M Serial Interface: Transmit Latency ............................................................... 136 10.5.11 10M Media Independent Interface: Transmit Latency .......................................... 137 10.5.12 MII / 100M Stream Interface: Transmit Latency ................................................... 138 10.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) ...
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ICS1893 - Release Revision History • The initial release of this document, Rev A, was dated August 5, 1999. • Rev B was dated September 10, 1999. The following list also indicates what changes were made. – Page 1. Document ...
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ICS1893 Data Sheet - Release • This release of this document, Rev C, is dated May 22, 2000. Change bars indicate where all changes are made. (For an explanation of change bars, see the Change Bar note on this page.) ...
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ICS1893 - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute ...
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ICS1893 Data Sheet - Release Table 1-1. Abbreviations and Acronyms (Continued) Abbreviation / Acronym OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893 is a physical-layer device, also referred ‘ PHY’ or ‘ ...
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ICS1893 - Release Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Code groups Colon (:) Numbers Pin (or signal) names Registers ICS1893 ...
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ICS1893 Data Sheet - Release Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Symbols Terms: ‘ set’ , ‘ active’ , ‘ asserted’ , Terms: ‘ cleared’ , ‘ de-asserted’ , ‘ inactive’ Terms: ‘ twisted-pair receiver’ Terms: ‘ ...
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ICS1893 - Release Chapter 3 ICS1893 Enhanced Features The ICS1893 is an enhanced version of the ICS1890. In contrast to the ICS1890, the ICS1893 offers significant improvements in both performance and features while maintaining backward compatibility. The specific differences between ...
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ICS1893 Data Sheet - Release Table 3-1. Summary of Differences between ICS1890 and ICS1893 Registers Register. ICS1890 Bit(s) Function 1.6 Reserved 3.9:4 Model Number 3.3:0 Revision Number 6.2 Next Page Able 7.15:0 Not applicable (N/A) 8.15:0 N/A 9.15:0 IEEE reserved. ...
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ICS1893 - Release Chapter 4 Overview of the ICS1893 The ICS1893 is a stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control)/Repeater Interface, converts them into a serial bit stream, encodes them, and transmits ...
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ICS1893 Data Sheet - Release 4.1 100Base-TX Operation During 100Base-TX data transmission, the ICS1893 accepts packets from a MAC/repeater and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893 encapsulates each MAC/repeater frame, including the ...
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ICS1893 - Release Chapter 5 Operating Modes Overview The ICS1893 operating modes and interfaces are configurable with one of two methods. The HW/SW (hardware/software) pin determines which method the ICS1893 is to use, either its hardware pins or its register ...
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ICS1893 Data Sheet - Release 5.1 Reset Operations This section first discusses reset operations in general and then specific ways in which the ICS1893 can be configured for various reset options. 5.1.1 General Reset Operations The following reset operations apply ...
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ICS1893 - Release 5.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1893 can be reset: • Hardware reset (using the RESETn pin) • Power-on reset (applying power to the ICS1893) • Software reset (using Control ...
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ICS1893 Data Sheet - Release 5.1.2.3 Software Reset Entering Software Reset Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit 0.15. When this write occurs, the ICS1893 enters the reset state ...
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ICS1893 - Release 5.3 Automatic Power-Saving Operations The ICS1893 has power-saving features that automatically minimize its total power consumption while it is operating. Table 5-1 lists the ICS1893 automatic power-saving features for the various modes. Table 5-1. Automatic Power-Saving Features, ...
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ICS1893 Data Sheet - Release 5.5 100Base-TX Operations The ICS1893 100Base-TX mode provides 100Base-TX physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893 is a 100M translator between a MAC/repeater and the ...
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ICS1893 - Release Chapter 6 Interface Overviews The ICS1893 MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 6.1, “ MII Data Interface” • Section ...
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ICS1893 Data Sheet - Release 6.1 MII Data Interface The most common configuration for an ICS1893’ s MAC/Repeater Interface is the Medium Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. When the ICS1893 MAC/Repeater Interface is configured ...
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ICS1893 - Release 6.2 100M Symbol Interface The 100M Symbol Interface has a primary objective of supporting 100Base-TX repeater applications for which the repeater requires only recovered parallel data and for which the repeater provides all the necessary framing and ...
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ICS1893 Data Sheet - Release Table 6-1 lists the pin mappings for the ICS1893 100M Symbol Interface mode. Table 6-1. Pin Mappings for 100M Symbol Interface Mode Default 10M / 100M MII Pin Names COL No connect. [Because the MAC/repeater ...
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ICS1893 - Release 6.3 10M Serial Interface When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1893 and the MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial Interface configuration is ...
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ICS1893 Data Sheet - Release Table 6-2 lists the pin mappings for the ICS1893 10M Serial Interface mode. Table 6-2. Pin Mappings for 10M Serial Interface Mode Default 10M / 100M MII Pin Names COL 10COL CRS 10CRS MDC MDC ...
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ICS1893 - Release 6.4 Serial Management Interface The ICS1893 provides an ISO/IEC compliant, two-wire Serial Management Interface as part of its MAC/Repeater Interface. This Serial Management Interface is used to exchange control, status, and configuration information between a Station Management ...
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ICS1893 Data Sheet - Release 6.5.1 Twisted-Pair Transmitter Interface The twisted-pair transmitter driver uses an H-bridge configuration, which requires that the transmit transformer not have a choke on the chip side. ICS suggests any of the following for the H-bridge: ...
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ICS1893 - Release 6.5.2 Twisted-Pair Receiver Interface Figure 6-2 shows the design for the ICS1893 twisted-pair receiver interface. • Two 56.2 1% resistors are in series, with the center bypassed to ground with a 0.1- F bypass capacitor. • No ...
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ICS1893 Data Sheet - Release 6.6 Clock Reference Interface The REF_IN pin provides the ICS1893 Clock Reference Interface. The ICS1893 requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to ...
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ICS1893 - Release 6.8 Status Interface The ICS1893 LSTA pin provides a Link Status, and its LOCK pin provides a Stream Cipher Locking Status. In addition, as listed in Table results of continual link monitoring by providing signals that are ...
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ICS1893 Data Sheet - Release Figure 6-3 shows typical biasing and LED connections for the ICS1893. Figure 6-3. ICS1893 LED - PHY Address P4RD P3TD 64 62 REC TRANS 10K 10K This circuit decodes to PHY address = 1. Note: ...
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ICS1893 - Release Chapter 7 Functional Blocks This chapter discusses the following ICS1893 functional blocks. • Section 7.1, “ Functional Block: Media Independent Interface” • Section 7.2, “ Functional Block: Auto-Negotiation” • Section 7.3, “ Functional Block: 100Base-X PCS and ...
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ICS1893 Data Sheet - Release 7.1 Functional Block: Media Independent Interface All ICS1893 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the ICS1893 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) ...
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ICS1893 - Release 7.2 Functional Block: Auto-Negotiation The auto-negotiation logic of the ICS1893 has the following main functions: • To determine the capabilities of the remote link partner, (that is, the device at the other end of the link segment’ ...
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ICS1893 Data Sheet - Release 7.2.1 Auto-Negotiation General Process The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T ...
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ICS1893 - Release 7.2.2 Auto-Negotiation: Parallel Detection The ICS1893 supports parallel detection therefore compatible with networks that do not support the auto-negotiation process. When enabled, the Auto-Negotiation sublayer can detect legacy 10Base-T link partners as well as 100Base-TX ...
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ICS1893 Data Sheet - Release 7.2.4 Auto-Negotiation: Reset and Restart If enabled, execution of the ICS1893 auto-negotiation process occurs at power-up and upon management request. There are two primary ways to begin the Auto-Negotiation state machine: • ICS1893 reset • ...
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ICS1893 - Release Auto-Negotiation Link Partner Ability Register and determine the highest-performance operating mode in common with the capabilities it is advertising. The ISO/IEC-defined priority table determines the established link type simpler alternative, the STA can read the ...
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ICS1893 Data Sheet - Release 7.3 Functional Block: 100Base-X PCS and PMA Sublayers The ICS1893 is fully compliant with clause 24 of the ISO/IEC specification, which defines the 100Base-X Physical Coding sublayer (PCS) and Physical Medium Attachment (PMA) sublayers. 7.3.1 ...
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ICS1893 - Release 7.3.3 PCS/PMA Transmit Modules Both the PCS and PMA sublayers have Transmit modules. 7.3.3.1 PCS Transmit Module The ICS1893 PCS Transmit module accepts nibbles from the MAC/Repeater Interface and converts the nibbles into 5-bit ‘ code groups’ ...
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ICS1893 Data Sheet - Release 7.3.4 PCS/PMA Receive Modules Both the PCS and PMA sublayers have Receive modules. 7.3.4.1 PCS Receive Module The ICS1893 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA ...
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ICS1893 - Release 7.3.5 PCS Control Signal Generation For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect signal (COL). The CRS control signals is generated as follows: 1. When a logic ...
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ICS1893 Data Sheet - Release 7.4 Functional Block: 100Base-TX TP-PMD Operations The ICS1893 supports both 10Base-T and 100Base-TX operations. For 100Base-TX operations, the TP-PMD module performs stream-cipher scrambling/descrambling and MLT-3 encoding/decoding (3-level, multi-level transition) in compliance with the ANSI Standard ...
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ICS1893 - Release 7.4.4 100Base-TX Operation: Adaptive Equalizer The ICS1893 has a TP-PMD sublayer that uses adaptive equalization circuitry to compensate for signal amplitude and phase distortion incurred from the transmission medium data rate of 100 Mbps, the ...
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ICS1893 Data Sheet - Release 7.4.7 100Base-TX Operation: Auto Polarity Correction The ICS1893 can sense and then automatically correct a signal polarity that is reversed on its Twisted-Pair Receiver inputs. A signal polarity reversal occurs when the input signals on ...
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... The 10Base-T and 100Base-TX operations differ as follows. 10Base-T operations are fundamentally simpler than 100Base-TX operations. The data rate is slower, requiring less encoding than 100Base-TX operations. In addition, the bandwidth requirements (and therefore the line attenuation issues) are not as severe as with 100-MHz operations. Consequently, when an ICS1893 is set for 10Base-T operations, it requires fewer internal circuits in contrast to 100Base-TX operations ...
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ICS1893 Data Sheet - Release 7.5.4 10Base-T Operation: Idle An ICS1893 transmits Normal Link Pulses (that is, 10Base-T Idles) on its MDI in the absence of data (that is, when the MAC/repeater is not requiring it to transmit any data). ...
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ICS1893 - Release Note ICS1893 receives ‘ valid data’ when its Twisted-Pair Receiver phase-locked loop can acquire lock and extract the receive clock from the incoming data stream for a minimum of three consecutive bit times. 2. When ...
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ICS1893 Data Sheet - Release 7.5.9 10Base-T Operation: Jabber The ICS1893 has an ISO/IEC compliant Jabber Detection Function that, when enabled, monitors the data stream sent to its Twisted-Pair Transmitter to ensure that it does not exceed the 10Base-T Jabber ...
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ICS1893 - Release 7.5.11 10Base-T Operation: Twisted-Pair Transmitter The 10Base-T Twisted-Pair Transmitter is functionally similar to the 100Base-TX Twisted-Pair Transmitter. The primary differences are in the data rate and signaling, as specified in the ISO/IEC specifications. For more information, see ...
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ICS1893 Data Sheet - Release 7.6 Functional Block: Management Interface As part of the MAC/Repeater Interface, the ICS1893 provides a two-wire serial management interface which complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used to ...
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ICS1893 - Release 7.6.2.1 Management Frame Preamble The ICS1893 continually monitors its serial management interface for either valid data or a Management Frame (MF) Preamble, based upon the setting of the MF Preamble Suppression bit, 1.6. When the MF Preamble ...
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... Management Frame Data A valid management frame includes a 16-bit Data field for exchanging the register contents between the ICS1893 and the STA. All Management Registers are 16 bits wide, matching the width of the Data field. During a transaction that is a: • Read, (OP is 10b) the ICS1893 obtains the contents of the register identified in the REGAD field and returns this Data to the STA synchronously with its MDC signal. • ...
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ICS1893 - Release Chapter 8 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, the STA Read/Write Access ...
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ICS1893 Data Sheet - Release 8.1 Introduction to Management Register Set This section explains in general terms the Management Register set discussed in this chapter. (For a summary of the Management Register set, see 8.1.1 Management Register Set Outline This ...
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ICS1893 - Release 8.1.2 Management Register Bit Access The ICS1893 Management Registers include one or more of the following types of bits: Table 8-3. Description of Management Register Bit Types Management Register Bit Types Symbol Read-Only Command Override Write Read/Write ...
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ICS1893 Data Sheet - Release 8.1.4 Management Register Bit Special Functions This section discusses the types of special functions for the Management Register bits. 8.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to record an ...
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ICS1893 - Release 8.2 Register 0: Control Register Table 8-5 lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes of the ICS1893. • The Control Register is accessible through the MII Management ...
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ICS1893 Data Sheet - Release 8.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1893. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling the Twisted-Pair ...
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ICS1893 - Release 8.2.5 Low Power Mode (bit 0.11) This bit provides one way to control the ICS1893 low-power mode function. When bit 0.11 is logic: • Zero, there is no impact to ICS1893 operations. • One, the ICS1893 enters ...
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ICS1893 Data Sheet - Release 8.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1893 Duplex Mode. Its operation depends on several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). ...
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ICS1893 - Release 8.3 Register 1: Status Register Table 8-6 lists the Status Register bits. These 16 bits of data provide an interface between the ICS1893 and an STA. There are two types of status bits: some report the capabilities ...
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ICS1893 Data Sheet - Release 8.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1893 can support 100Base-TX, full-duplex operations. The ISO/IEC specification requires that the ICS1893 must set bit 1.14 to logic: • ...
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ICS1893 - Release 8.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1893 returns a logic zero. • Writes a reserved bit, the STA must use ...
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ICS1893 Data Sheet - Release 8.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893 sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ...
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ICS1893 - Release 8.3.11 Link Status (bit 1.2) The purpose of this bit 1.2 (which is also accessible through the QuickPoll Detailed Status Register, bit 17. determine if an established link is dropped, even momentarily. To indicate a ...
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ICS1893 Data Sheet - Release 8.4 Register 2: PHY Identifier Register Table 8-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC ...
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ICS1893 - Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is formed by expressing each ...
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ICS1893 Data Sheet - Release 8.5 Register 3: PHY Identifier Register Table 8-9 lists the bits for PHY Identifier Register (Register 3), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC ...
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ICS1893 - Release 8.5.2 Manufacturer's Model Number (bits 3.9:4) The model number for the ICS1893 is 4 (decimal stored in bit 3.9:4 as 00100b. 8.5.3 Revision Number (bits 3.3:0) Table 8-10 lists the valid ICS1893 revision numbers, which ...
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ICS1893 Data Sheet - Release 8.6 Register 4: Auto-Negotiation Register Table 8-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the ICS1893 capabilities that it wants to advertise to its remote link partner. During ...
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ICS1893 - Release 8.6.2 IEEE Reserved Bit (bit 4.14) The ISO/IEC specification reserves this bit for future use. However, the ISO/IEC Standard also defines bit 4.14 as the Acknowledge bit. When this reserved bit is read by an STA, the ...
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ICS1893 Data Sheet - Release 8.6.5 Technology Ability Field (bits 4.9:5) When its Auto-Negotiation sublayer is enabled, the ICS1893 transmits its link capabilities to its remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5 determine ...
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ICS1893 - Release 8.6.5.2 Technology Ability Field: Software Mode In Software mode (that is, the HW/SW pin is logic one), these TAF bits are Command Override Write bits. The default value of these bits depends on the signal level on ...
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ICS1893 Data Sheet - Release 8.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 8-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the remote link ...
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ICS1893 - Release 8.7.2 Acknowledge (bit 5.14) The ISO/IEC specification defines bit 5.14 as the Acknowledge bit. When this bit is a: • Zero, it indicates that the remote link partner has not received the ICS1893 Link Control Word. • ...
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ICS1893 Data Sheet - Release 8.8 Register 6: Auto-Negotiation Expansion Register Table 8-13 lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the Auto-Negotiation process. Note: For an explanation of acronyms used in Table 8-13. Auto-Negotiation ...
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ICS1893 - Release 8.8.2 Parallel Detection Fault (bit 6.4) The ICS1893 sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1893 cannot disseminate the technology being used by ...
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ICS1893 Data Sheet - Release 8.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 8-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during ...
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ICS1893 - Release 8.9.1 Next Page (bit 7.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features ...
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ICS1893 Data Sheet - Release 8.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 8-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word ...
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ICS1893 - Release 8.10.1 Next Page (bit 8.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features ...
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ICS1893 Data Sheet - Release 8.11 Register 16: Extended Control Register Table 8-16 lists the bits for the Extended Control Register, which the ICS1893 provides to allow an STA to customize the operations of the device. Note: 1. For an ...
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ICS1893 - Release 8.11.1 Command Override Write Enable (bit 16.15) The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write (CW) bits located throughout the MII Register set. A two-step process is required ...
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ICS1893 Data Sheet - Release 8.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893 to transmit symbols that are typically classified as invalid. The purpose of this test bit ...
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ICS1893 - Release 8.12 Register 17: Quick Poll Detailed Status Register Table 8-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed status of the ICS1893 ...
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ICS1893 Data Sheet - Release 8.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘ selected technology’ the ICS1893 is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. ...
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ICS1893 - Release 8.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11) The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually examines the state of the Auto-Negotiation ...
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ICS1893 Data Sheet - Release 8.12.5 100Base PLL Lock Error (bit 17.9) The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893 has ever experienced a PLL Lock Error. A PLL Lock Error occurs when the ...
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ICS1893 - Release 8.12.8 Halt Symbol (bit 17.6) The Halt Symbol bit indicates to an STA the detection of a Halt Symbol in a 100Base data stream by the ICS1893. During reception of a valid packet, the ICS1893 examines each ...
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ICS1893 Data Sheet - Release 8.12.12 Jabber Detect (bit 17.2) Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has occurred. This bit is a 10Base-T function. 8.12.13 Remote Fault (bit 17.1) ...
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ICS1893 - Release 8.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893 activity while the ICS1893 is operating in 10Base-T mode. Note: 1. For an explanation of ...
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ICS1893 Data Sheet - Release 8.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the ...
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ICS1893 - Release 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state ...
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ICS1893 Data Sheet - Release 8.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893 operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to ...
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ICS1893 - Release 8.14.1 Node/Repeater Configuration (bit 19.15) The Node/Repeater Configuration bit directly indicates the state of the NOD/REP input pin. When this bit is logic: • Zero, the NOD/REP input pin is pulled down, which instructs the operation code ...
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ICS1893 Data Sheet - Release 8.14.5 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893 provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN signals to a high-impedance state. When this bit is set to ...
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ICS1893 - Release Chapter 9 Pin Diagram, Listings, and Descriptions 9.1 ICS1893 Pin Diagram NOD/REP 1 10/100SEL 2 TP_CT 3 VSS 4 TP_TXP 5 TP_TXN 6 VDD 7 VDD 8 10TCSR 9 100TCSR 10 VSS 11 VSS 12 TP_RXP 13 ...
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ICS1893 Data Sheet - Release 9.2 ICS1893 Pin Listings Table 9-1 lists the ICS1893 pins by pin number. Table 9-1. ICS1893 Pins, by Pin Number Pin Pin Name No. 1 NOD/REP 2 10/100SEL 3 TP_CT 4 VSS 5 TP_TXP 6 ...
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ICS1893 - Release 9.3 ICS1893 Pin Descriptions The tables in this section list the ICS1893 pins by their functional grouping. 9.3.1 Transformer Interface Pins Table 9-2 lists the pins for the transformer interface group of pins. Table 9-2. Transformer Interface ...
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ICS1893 Data Sheet - Release 9.3.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins Table 9-3 lists the pins for the multi-function group of pins (that is, the multiplexed PHY Address / LED pins). Note: 1. During either a power-on ...
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ICS1893 - Release Table 9-3. PHY Address and LED Pins Pin Pin Pin Name Number Type P1CL 59 Input or Output ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description PHY (Address Bit Collision ...
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ICS1893 Data Sheet - Release Table 9-3. PHY Address and LED Pins Pin Pin Pin Name Number Type P2LI 60 Input or Output P3TD 62 Input or Output ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893 - Release Table 9-3. PHY Address and LED Pins Pin Pin Pin Name Number Type P4RD 64 Input or Output ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description PHY (Address Bit Receive ...
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ICS1893 Data Sheet - Release 9.3.3 Configuration Pins Table 9-4 lists the configuration pins. Table 9-4. Configuration Pins Pin Pin Name Number Type 10/100SEL 2 Input or Output 10TCSR 9 Input 100TCSR 10 Input ANSEL 26 Input or Output DPXSEL ...
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ICS1893 - Release Table 9-4. Configuration Pins (Continued) Pin Pin Name Number Type HW/SW 23 Input LOCK 27 Output LSTA 21 Output MII/SI 19 Input NOD/REP 1 Input REF_IN 53 Input REF_OUT 52 Input RESETn 18 Input ICS1893 Rev C ...
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ICS1893 Data Sheet - Release 9.3.4 MAC/Repeater Interface Pins This section lists pin descriptions for each of the following interfaces • Section 9.3.4.1, “ MAC/Repeater Interface Pins for Media Independent Interface” • Section 9.3.4.2, “ MAC/Repeater Interface Pins for 100M ...
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ICS1893 - Release Table 9-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type MDIO 30 Input/ Output RXCLK 38 Output ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description Management ...
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ICS1893 Data Sheet - Release Table 9-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type RXD0, 35, Output RXD1, 34, RXD2, 33, RXD3 32 RXDV 36 Output RXER 39 Output RXTRI 41 Input TXCLK ...
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ICS1893 - Release Table 9-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type TXEN 44 Input TXER 42 Input ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description Transmit Enable. ...
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ICS1893 Data Sheet - Release 9.3.4.2 MAC/Repeater Interface Pins for 100M Symbol Interface Table 9-6 lists the MAC/Repeater Interface pin descriptions for the 100M Symbol Interface. Table 9-6. MAC/Repeater Interface Pins: 100M Symbol Interface MII Pin 100M Pin Name Symbol ...
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ICS1893 - Release Table 9-6. MAC/Repeater Interface Pins: 100M Symbol Interface (Continued) MII Pin 100M Pin Name Symbol No. Pin Name RXCLK SRCLK 38 ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Type Output (Symbol) Receive ...
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ICS1893 Data Sheet - Release Table 9-6. MAC/Repeater Interface Pins: 100M Symbol Interface (Continued) MII Pin 100M Pin Name Symbol No. Pin Name RXD0, SRD0, 35, RXD1, SRD1, 34, RXD2, SRD2, 33, RXD3 SRD3 32 RXDV – 36 RXER SRD4 ...
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ICS1893 - Release 9.3.4.3 MAC/Repeater Interface Pins for 10M Serial Interface Table 9-7 lists the MAC/Repeater Interface pin descriptions for the 10M Serial Interface. Table 9-7. MAC/Repeater Interface Pins: 10M Serial Interface MII Pin 100M Pin Name Symbol No. Pin ...
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ICS1893 Data Sheet - Release Table 9-7. MAC/Repeater Interface Pins: 10M Serial Interface (Continued) MII Pin 100M Pin Name Symbol No. Pin Name RXDV 10RXDV 36 RXER – 39 RXTRI 41 TXCLK 10TCLK 43 TXD0 10TD 45 TXD1, – 46, ...
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ICS1893 - Release 9.3.5 Reserved Pins Table 9-8 lists the reserved pins. Table 9-8. Reserved Pins Pin Pin Pin Name Number Type NC 20 – ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description No Connect. ...
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ICS1893 Data Sheet - Release 9.3.6 Ground and Power Pins Table 9-9 lists the ground and power pins. Table 9-9. Ground and Power Pins Pin Name Pin Number VSS 4 VSS 11 VSS 12 VSS 17 VSS 22 VSS 28 ...
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ICS1893 - Release Chapter 10 DC and AC Operating Conditions 10.1 Absolute Maximum Ratings Table 10-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893. These ratings, which are standard values for ICS commercially rated parts, ...
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ICS1893 Data Sheet - Release 10.3 Recommended Component Values Table 10-3. Recommended Component Values for ICS1893 Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std 802.3 requirements that drive the tolerance ...
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ICS1893 - Release 10.4 DC Operating Characteristics This section lists the ICS1893 DC operating characteristics. 10.4.1 DC Operating Characteristics for Supply Current Table 10-4 lists the DC operating characteristics for the supply current to the ICS1893 under various conditions. Note: ...
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ICS1893 Data Sheet - Release 10.4.3 DC Operating Characteristics for REF_IN Table 10-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 10-6. 3.3-V DC Operating Characteristics for REF_IN ...
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ICS1893 - Release 10.5 Timing Diagrams 10.5.1 Timing for Clock Reference In (REF_IN) Pin Table 10-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. Note: The ...
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ICS1893 Data Sheet - Release 10.5.2 Timing for Transmit Clock (TXCLK) Pins Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 10-3 shows the timing diagram for the time ...
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ICS1893 - Release 10.5.3 Timing for Receive Clock (RXCLK) Pins Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 10-4 shows the timing diagram for the time periods. Table ...
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ICS1893 Data Sheet - Release 10.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing Table 10-11 lists the significant time periods for the 100M MII / 100M Stream Interface synchronous transmit timing. The time periods consist of timings of ...
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ICS1893 - Release 10.5.5 10M MII: Synchronous Transmit Timing Table 10-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • ...
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ICS1893 Data Sheet - Release 10.5.6 MII / 100M Stream Interface: Synchronous Receive Timing Table 10-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on ...
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ICS1893 - Release 10.5.7 MII Management Interface Timing Table 10-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 10-14. MII Management Interface Timing Time ...
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ICS1893 Data Sheet - Release 10.5.8 10M Serial Interface: Receive Latency Table 10-15 lists the significant time periods for the 10M Serial Interface timing. The time periods consist of timings of signals on the following pins: • TP_RX (the MDI ...
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ICS1893 - Release 10.5.9 10M Media Independent Interface: Receive Latency Table 10-16 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, the MII ...
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ICS1893 Data Sheet - Release 10.5.10 10M Serial Interface: Transmit Latency Table 10-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods consist of timings of signals on the following pins: • 10TXEN (the ...
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ICS1893 - Release 10.5.11 10M Media Independent Interface: Transmit Latency Table 10-18 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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ICS1893 Data Sheet - Release 10.5.12 MII / 100M Stream Interface: Transmit Latency Table 10-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following ...
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ICS1893 - Release 10.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-20 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN ...
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ICS1893 Data Sheet - Release 10.5.14 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-21 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893 - Release 10.5.15 100M MII / 100M Stream Interface: Receive Latency Table 10-22 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the following ...
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ICS1893 Data Sheet - Release 10.5.16 100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion Table 10-23 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that ...
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ICS1893 - Release 10.5.17 Reset: Power-On Reset Table 10-24 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 10-18 shows the timing diagram ...
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... Table 10-25. Hardware Reset and Power-Down Timing Time Period t1 RESETn Active to Device Isolation and Initialization t2 Minimum RESETn Pulse Width t3 RESETn Released to TXCLK Valid Figure 10-19. Hardware Reset and Power-Down Timing Diagram REF_IN RESETn TXCLK Valid ...
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ICS1893 - Release 10.5.19 10Base-T: Heartbeat Timing (SQE) Table 10-26 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • TXEN • ...
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ICS1893 - Release 10.5.20 10Base-T: Jabber Timing Table 10-27 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and TP_TXN) • ...
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... Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 10-28. 10Base-T Normal Link Pulse Timing Time Period t1 Normal Link Pulse Width t2 Normal Link Pulse to Normal Link Pulse Period Figure 10-22. 10Base-T Normal Link Pulse Timing Diagram TP_TXP ...
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... Period t1 Clock/Data Pulse Width t2 Clock Pulse-to-Data Pulse Timing t3 Clock Pulse-to-Clock Pulse Timing t4 Fast Link Pulse Burst Width t5 Fast Link Pulse Burst to Fast Link Pulse Burst t6 Number of Clock/Data Pulses in a Burst Figure 10-23. Auto-Negotiation Fast Link Pulse Timing Diagram Clock Pulse ...
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... ICS1893 physical dimensions, which are shown in Table 11-1. ICS1893 Physical Dimensions Sym- Description bol A Full Package Height A1 Package Standoff A2 Package Thickness b Lead Width with Plate c Lead Height with Plate D Tip-to-Tip Width D1 Body Width E Tip-to-Tip Width E1 Body Width e Lead Pitch ...
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Figure 11-1. ICS1893 Physical Dimensions ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device ...
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... ICS1893 - Release Chapter 12 Ordering Information Figure 12-1 shows ordering information for the ICS1893 package: • ICS1893Y-10LF and ICS1893YI-10LF (industrial temp.) Figure 12-1. ICS1893 Ordering Information Y -10 ICS 1893 ICS1893 Rev C 6/6/ Tape and Reel Lead (Pb) Free, RoHS compliant Package Type Y- TQFP (Thin Quad Flat Pack) ...
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Integrated Circuit Systems, Inc. Corporate Headquarters: Silicon Valley: Web Site: ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device ...