1893YI-10LFT IDT, 1893YI-10LFT Datasheet - Page 34

• Manufacturer Part Number: 1893YI-10LFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893YI-10LFT

• Rohs: yes
• Part # Aliases: ICS1893YI-10LFT

6.6 Clock Reference Interface
6.7 Configuration Interface
ICS1893 Rev C 6/6/00
The REF_IN pin provides the ICS1893 Clock Reference Interface. The ICS1893 requires a single clock
reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to meet the
interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The
ICS1893 supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to
REF_IN is CMOS (10% to 90% VDD), not TTL.
The following Configuration and Status Interface pins allow the ICS1893 to be completely configured and
controlled in hardware mode:
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•
•
•
•
•
•
•
These pins allow the ICS1893 to accommodate the following:
•
•
•
•
In addition to the ISO/IEC-specified, MII control signals, the ICS1893 provides RXTRI, which is a tri-state
enable pin for the MII receive data path. When this pin is active (that is, a logic one), the following pins are
tri-stated:
•
•
•
•
Functionally, the RXTRI pin affects the MII receive channel in the same way as the Control Register’ s
isolate bit, bit 0.10. (The isolate bit also affects the transmit data path.) The ICS1893 can tri-state these
seven signals for all five types of MAC/Repeater Interface configurations, not just the MII interface.
10/100SEL
ANSEL
DPXSEL
HW/SW
MII/SI
NOD/REP
RESETn
RXTRI
10M or 100M operations
Four MAC/Repeater Interface configurations:
Node or repeater applications
Full-duplex or half-duplex data links
RXCLK
RXD[3:0]
RXDV
RXER
– 10M MII
– 100M MII
– 100M Symbol
– 10M Serial
ICS1893 Data Sheet - Release
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
34
Chapter 6 Interface Overviews
June, 2000