1893YI-10LFT IDT, 1893YI-10LFT Datasheet - Page 139

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1893YI-10LFT

Manufacturer Part Number
1893YI-10LFT
Description
Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
Manufacturer
IDT
Datasheet

Specifications of 1893YI-10LFT

Rohs
yes
Part # Aliases
ICS1893YI-10LFT
10.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
ICS1893 Rev C 6/6/00
Table 10-20
half-duplex transmission. The time periods consist of timings of signals on the following pins:
Figure 10-14
Table 10-20. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Figure 10-14. 100M MII Carrier Assertion/De-Assertion Timing Diagram
TXEN
TXCLK
CRS
Period
Time
TXEN
TXCLK
CRS
t1
t2
ICS1893 - Release
TXEN Sampled Asserted to CRS Assert
TXEN De-Asserted to CRS De-Asserted
lists the significant time periods for the 100M MII carrier assertion/de-assertion during
shows the timing diagram for the time periods.
(Half-Duplex Transmission Only)
t1
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Parameter
139
t2
Chapter 10 DC and AC Operating Conditions
Condi-
tions
Min.
0
0
Typ.
3
3
Max.
4
4
June, 2000
Bit times
Bit times
Units

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