1893YI-10LF IDT, 1893YI-10LF Datasheet - Page 46

• Manufacturer Part Number: 1893YI-10LF
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893YI-10LF

• Rohs: yes
• Part # Aliases: ICS1893YI-10LF

7.3.4 PCS/PMA Receive Modules
7.3.4.1
7.3.4.2
ICS1893 Rev C 6/6/00
Both the PCS and PMA sublayers have Receive modules.
The ICS1893 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA
sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and
then processes the data to detect the presence of a carrier.
When a link is in the idle state, the PCS Receive module receives IDLE symbols. (All bits are logic one.)
Upon receiving two non-contiguous zeros in the bit stream, the PCS Receive module examines the
ensuing bits and attempts to locate the Start-of-Stream Delimiter (SSD), that is, the /J/K/ symbols.
Upon verification of a valid SSD, the PCS Receive module substitutes the first two standard nibbles of a
Frame Preamble for the detected SSD. In addition, the PCS Receive module uses the SSD to begin
framing the ensuing data into 5-bit code symbols. The final PCS Receive module performs 4B/5B decoding
on the symbols and then synchronously passes the resulting nibbles to the MAC/Repeater Interface.
The Receive state machine continues to accept PMA data, convert it from serial to parallel format, frame it,
decode it, and pass it to the MAC/Repeater Interface. During this time, the Receive state machine
alternates between Receive and Data States. It continues this process until detecting one of the following:
•
•
•
Upon receipt of an ESD, the Receive state machine returns to the IDLE state without passing the ESD to
the MAC/Repeater Interface. Detection of an error forces the Receive state machine to assert the receive
error signal (RX_ER) and wait for the next symbol. If the ICS1893 Receive state machine detects a
premature end, it forces the assertion of the RX_ER signal, sets the Premature End bit (bit 17.5) to logic
one, and transitions to the IDLE State.
The ICS1893 has a PMA Receive module that provides the following functions:
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•
•
PCS Receive Module
PMA Receive Modules
An End-of-Stream Delimiter (ESD, that is, the /T/R/ symbols)
An error
A premature end (IDLEs)
NRZI Decoding
The Receive module performs the NRZI decoding on the serial bit stream received from the Twisted-Pair
Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a unipolar, positive, binary
format that the PMA subsequently passes to the PCS.
Receive Clock Recovery
The Receive Clock Recovery function consists of a phase-locked loop (PLL) that operates on the serial
data stream received from the PMD sublayer. This PLL automatically synchronizes itself to the clock
encoded in the serial data stream and then provides both a recovered clock and data stream to the PCS.
Link Monitoring
– The ICS1893’ s PMA Link Monitoring function observes the Receive Clock PLL. If the Receive Clock
– In addition, the ICS1893’ s PMA Link Monitor function continually audits the state of the connection
ICS1893 Data Sheet - Release
PLL cannot acquire ‘ lock’ on the serial data stream, it asserts an error signal. The status of this error
signal can be read in the QuickPoll Detailed Status Register’ s PLL Lock Error bit (bit 17.9). This bit is
a latching high (LH) bit. (For more information on latching high and latching low bits, see
8.1.4.1, “ Latching High Bits”
with the remote link partner. It asserts a receive channel error if a receive signal is not detected or if
a PLL Lock Error occurs. These errors, in turn, generate a link fault and force the link monitor
function to clear both the Status Register’ s Link Status bit (bit 1.2) and the QuickPoll Detailed Status
Register’ s Link Status bit (bit 17.0).
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
and
Section 8.1.4.2, “ Latching Low Bits”
46
.)
Chapter 7 Functional Blocks
Section
June, 2000