73S8010R-IM/F1 Maxim Integrated, 73S8010R-IM/F1 Datasheet - Page 14

• Manufacturer Part Number: 73S8010R-IM/F1
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010R-IM/F1

• Rohs: yes

73S8010R Data Sheet
3.2
A fast-mode 400 kHz I
status of the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0,
SAD1, and SAD2. This allows up to 8 devices to be connected in parallel. Table 9 lists the device
address selections for the SAD2:0 settings.
Table 10 describes the Control Register Bits.
14
Name
Start/Stop
Warm reset
5 V and 3 V
Clock Stop
Clock Stop Level
Clksel1
Clksel2
I/O enable
System Controller Interface (I
Bit 0 of the I
Bit
0
1
2
3
4
5
6
7
2
2
C bus slave interface is used for controlling the 73S8010R device and reading the
C address is the R/W bit. Refer to
Description
When set, initiates an activation and a cold reset procedure; when reset,
initiates a deactivation sequence.
When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute.
When set, V
0 = 0) and operating with 3 V (bit 2 =1), do not simultaneously set bit 2 =0.
When set, the card clock is stopped. Bit 4 determines the card clock stop
level.
When set, card clock stops high; when reset card clock stops low.
Bits 5 and 6 determine the clock rate to the card. See Table 11 for more
details.
I/O enable bit. When set, I/O is transferred on I/OUC; when reset I/O to
I/OUC is high impedance.
Bit Clksel2
Table 10: Control Register Description
SAD2
Table 11: Card Clock Rate Selection
0
0
1
1
Table 9: Device Address Selection
0
0
0
0
1
1
1
1
Power-on-reset value = 0x00
CC
SAD1
= 3 V; when reset, V
2
0
0
1
1
0
0
1
1
Bit Clksel1
C Bus)
0
1
0
1
SAD0
0
1
0
1
0
1
0
1
Figure 5
(7 bit) I
Address
CC
Clkin (Xtalin)
0x4C
Card Clock
0x4A
0x4E
0x40
0x42
0x44
0x46
0x48
= 5 V. When de-activating (setting bit
Clkin/8
Clkin/4
Clkin/2
and
2
C
Figure 6
for usage.
DS_8010R_022
Rev. 1.6