73S8010R-IM/F1 Maxim Integrated, 73S8010R-IM/F1 Datasheet - Page 15

• Manufacturer Part Number: 73S8010R-IM/F1
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010R-IM/F1

• Rohs: yes

DS_8010R_022
I
The I
condition, the master sends a slave address. This address is seven bits long followed by an eighth bit
which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control register. After
the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The master now starts sending the 8
bits of data to the control register during the DATA bits. After the DATA bits, the ‘zero’ ACK bit is sent to
the master by the device. The master should send the STOP condition after receiving this ACK bit.
Table 12 describes the Status Register bits.
I
The I
START condition, the master sends a slave address. This address is seven bits long followed by an eighth
bit which is an opcode bit (R/W) – a ‘one’ indicates the master will read data from the status register. After
the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The device now starts sending the 8-bit
status register data to the control register during the DATA bits. After the DATA bits, the ‘one’ ACK bit is
sent to the device by the master. The master should send the STOP condition after receiving the ACK bit.
Rev. 1.6
2
2
Name
PRES
PRESL
I/O
SUPL
PROT
MUTE
EARLY
ACTIVE
C-bus Write to Control Register
C-bus Read from Status Register
2
2
C-bus Read Command from the Status Register follows the format shown in Figure 6. After the
C-bus Write command to the control register follows the format shown in Figure 5. After the START
SDA
SCL
condition
START
Bit
0
1
2
3
4
5
6
7
Description
Set when the card is present (pin PRES is high); reset when the card is not present.
Set when the PRES pin changes state (rising/falling edge); reset when the status
register is read. Generates an interrupt when set.
Set when I/O is high; reset when I/O is low.
Set when a voltage fault is detected; reset when the status register is read.
Generates an interrupt when set.
Set when an over-current or over-heating fault has occurred during a card session;
reset when the status register is read. Generates an interrupt when set.
Set during ATR when the card has not answered during the ISO 7816-3 time
window (40000 card clock cycles); reset when the next session begins.
Set during ATR when the card has answered before 400 card clock cycles; reset
when the next session begins.
Set when the card is active (V
ADDRESS bits
MSB
1-7
Table 12: Status Register Description
Figure 5: I
LSB
R/W bit
Power On Reset = 0x04
8
2
C Bus Write Protocol
CC
ACK bit
is on); reset when the card is inactive.
9
MSB
DATA bits
1-8
LSB
ACK bit
9
73S8010R Data Sheet
condition
STOP
15