73S8010R-IM/F1 Maxim Integrated, 73S8010R-IM/F1 Datasheet - Page 20

• Manufacturer Part Number: 73S8010R-IM/F1
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010R-IM/F1

• Rohs: yes

73S8010R Data Sheet
3.9
The Interrupt is an active low interrupt. It is set low if any of the following internal faults are detected:
•
•
•
The interrupt will also be set if one of the following status bit conditions is detected:
•
•
•
•
When the interrupt is set low by the detection of one of the status bits, it is set high when the status bits
are read. (READ STATUS DONE) Figure 10 shows the interrupt operation resulting from the fault or
status bit conditions.
A power-on-reset event will reset all of the control and status registers to their default states. A V
event does not reset these registers, but it will signal an interrupt condition and by the action of the timer
that creates the interval “t
considered valid for V
20
READ STATUS DONE
V
V
V
Early ATR
Mute ATR
Card insert or card extract
Protection status from Over-current or Over-heating
CC
DD
PC
Interrupt
Start/Stop
STATUS BITS
fault
fault
fault
VCC
RST
CLK
ANY FAULT
IO
INT
t
t
1
3
Figure 10: Interrupt operation due to Fault and Status Conditions
= > .5 μs
= > 0.5 μs
DD
as low as 1.5 to 1.8 volts. At the lower range of V
1
,” not clearing the interrupt until V
t
1
Figure 9: Deactivation Sequence
t
t
2
4
= > 7.5 μs
= > 0.5 μs
t
2
t
3
t
4
DD
is valid for at least t
DD
fault, POR will be asserted.
1
. A V
DD
DS_8010R_022
fault can be
DD
Rev. 1.6
fault