73S8010R-IM/F1 Maxim Integrated, 73S8010R-IM/F1 Datasheet - Page 25

• Manufacturer Part Number: 73S8010R-IM/F1
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010R-IM/F1

• Rohs: yes

DS_8010R_022
Revision History
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
This Data Sheet is proprietary to Teridian Semiconductor Corporation (TSC) and sets forth design goals
for the described product. The data sheet is subject to change. TSC assumes no obligation regarding
future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation
(TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the
reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability
for applications assistance.
Rev. 1.6
Revision
1.0
1.1
1.3
1.5
1.6
7/1/2004
11/10/2004
10/26/2005
1/21/2008
8/28/2009
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
Date
TEL [phone], FAX [phone], http://www.teridian.com
First publication.
Make revisions to all references of “I/O” as it relates to the pins for the smart
card and microcontroller interfaces, i.e. IO -> I/O and IOUC -> I/OUC. This
is done to insure consistency and follow the designations used in ISO 7816.
Remove the MLP pin numbering in the pin description.
Correct the clock division table under CARD CLOCK.
Change the value of R2 on the typical application schematic. The original
value is 100 KΩ and the updated value is 10 KΩ. The PRES input has a
high impedance pull down resistor and the 100 KΩ for R2 is too high to
insure a valid logic level on this input.
Remove NDS references in application schematic.
Removed leaded package option, replaced 32QFN punched with SAWN,
updated 28SO dimension.
Changed dimension of bottom exposed pad on 32QFN mechanical package
figure.
Added Section 6, Related Documentation and Section 7, Contact
Information.
Formatted to the corporate style. Added document number.
Miscellaneous editorial changes.
Description
73S8010R Data Sheet
25