73S8010R-IM/F1 Maxim Integrated, 73S8010R-IM/F1 Datasheet - Page 21

• Manufacturer Part Number: 73S8010R-IM/F1
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010R-IM/F1

• Rohs: yes

DS_8010R_022
3.10 Warm Reset
The 73S8010R automatically asserts a warm reset to the card when instructed through bit 1 of the I
Control register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock
cycles. The Warm Reset bit is automatically reset when the card starts answering or when the card is
declared mute.
3.11 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the
activation sequencer enables the I/O reception state. See
details on when the I/O reception is enabled. The states of the I/OUC, AUX1UC, and AUX2UC are high
after power on reset.
When the control I/O enable bit (bit 7) of the control register is set, the first I/O line on which a falling edge
is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line
rising edge is detected, then both I/O lines return to their neutral state. The delay between these signals
is shown in Figure 12.
Rev. 1.6
Warm Reset
(bit 1)
RST
IO
IOUC
IO
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
t
t
t
1
2
3
> 1.5µs, Warm Reset Starts
= 42000 card clock cycles, End of Warm Reset
= Resets Warm Reset bit 1 when detected ATR or Mute
t
1
Figure 11: Warm Reset Operation
t
Figure 12: I/O Timing Diagram
IO_HL
t
IO_LH
t
t
IO_HL
IOuc_HL
t
2
= 100ns
Section 3.7 Activation Sequence
= 100ns
t
IOUC_HL
t
t
IO_LH
IOUC_LH
= 25ns
= 25ns
t
3
73S8010R Data Sheet
t
IOUC_LH
for more
2
C
21