PCAL9539AHF,128 NXP Semiconductors, PCAL9539AHF,128 Datasheet
PCAL9539AHF,128
Specifications of PCAL9539AHF,128
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PCAL9539AHF,128 Summary of contents
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PCAL9539A Low-voltage 16-bit I interrupt and reset Rev. 1 — 3 October 2012 1. General description The PCAL9539A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander with interrupt and reset for I simple solution when additional I/Os are needed ...
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... NXP Semiconductors 2. Features and benefits C-bus to parallel port expander Operating power supply voltage range of 1. 5.5 V Low standby current consumption: 1.5 A (typical 1.0 A (typical at 3 Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs ...
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... Ordering information Table 1. Ordering information Type number Topside mark PCAL9539AHF L39A PCAL9539APW PCAL9539A 3.1 Ordering options Table 2. Ordering options Type number Orderable part number PCAL9539AHF PCAL9539AHF,128 PCAL9539APW PCAL9539APW,118 4. Block diagram A0 A1 SCL SDA V DD RESET V SS Fig 1. PCAL9539A Product data sheet 2 16-bit I ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning RESET P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 V Fig 2. 5.2 Pin description Table 3. Symbol INT A1 RESET [2] P0_0 [2] P0_1 [2] P0_2 [2] P0_3 [2] P0_4 [2] P0_5 [2] P0_6 [2] P0_7 V SS [3] P1_0 [3] P1_1 [3] P1_2 [3] P1_3 [3] P1_4 [3] P1_5 PCAL9539A Product data sheet 2 16-bit I ...
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... NXP Semiconductors Table 3. Symbol [3] P1_6 [3] P1_7 A0 SCL SDA V DD [1] HWQFN24 package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors (Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with the lower four bits of the Command byte are used to point to the extended features of the device (Agile I/O). This register is write only. Fig 5. Table 4. Command byte Pointer register bits ...
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... NXP Semiconductors 6.2.2 Input port register pair (00h, 01h) The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect. ...
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... NXP Semiconductors 6.2.4 Polarity inversion register pair (04h, 05h) The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity is inverted in the Input register bit in this register is cleared (written with a ‘ ...
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... NXP Semiconductors 6.2.6 Output drive strength register pairs (40h, 41h, 42h, 43h) The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example, Port 0.7 is controlled by register 41 bits CC0.7 (bits [7:6]), Port 0.6 is controlled by register 41 CC0.6(bits [5:4]). The output drive level of the GPIO is programmed 00b = 0.25 ...
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... NXP Semiconductors cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port 0 register will read ‘1’. The next read of the input port 0 register bit 4 register should now read ‘0’. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state ...
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... NXP Semiconductors 6.2.9 Pull-up/pull-down selection register pair (48h, 49h) The I/O port can be configured to have a pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin. If the pull-up/pull-down feature is disconnected, writing to this register will have no effect on I/O pin. Typical value is 100 k ...
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... NXP Semiconductors 6.2.11 Interrupt status register pair (4Ch, 4Dh) These read-only registers are used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. ...
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... NXP Semiconductors 6.3 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above V If the I/O is configured as an output enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either V recommended levels for proper operation ...
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... NXP Semiconductors 6.4 Power-on reset When power (from applied to V PCAL9539A in a reset condition until V condition is released and the PCAL9539A registers and I initializes to their default states. After that the operating voltage for a power-reset cycle. See requirements”. 6.5 RESET input The RESET input can be asserted to initialize the system while keeping the V operating level ...
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... NXP Semiconductors 7. Bus transactions The PCAL9539A PCAL9539A through write and read commands using I lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ...
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SCL slave address SDA START condition R/W write to port data out from port 0 data out from port 1 Fig 7. Write ...
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... NXP Semiconductors 7.2 Reading the port registers In order to read data from the PCAL9539A, the bus master must first send the PCAL9539A address with the least significant bit set to a logic 0 (see “PCAL9539A device determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1 ...
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INT INT t t v(INT) rst(INT) SCL R/W slave address I0.x SDA ...
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DATA 00 t h(D) data into port 1 DATA 10 INT t t v(INT) rst(INT) SCL R/W slave address I0.x SDA ...
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DATA 01 data into port 1 DATA 10 INT t t v(INT) rst(INT) SCL R/W slave address I0.x SDA ...
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... NXP Semiconductors 8. Application design-in information kΩ MASTER CONTROLLER SCL SDA INT RESET V SS Device address configured as 1110 100X for this example. P0_0, P0_2, P0_3 configured as outputs. P0_1, P0_4, P0_5 configured as inputs. P0_6, P0_7 and (P1_0 to P1_7) configured as inputs. ...
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... NXP Semiconductors Fig 14. High value resistor in parallel with 8.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘ ...
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... NXP Semiconductors Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through V and will create noise (some radiated, but more critically Simultaneous Switching Noise (SSN)) ...
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... NXP Semiconductors Table 28. Recommended supply sequencing and ramp rates (unless otherwise noted). Not tested; specified by design. amb Symbol Parameter (dV/dt) fall rate of change of voltage f (dV/dt) rise rate of change of voltage r t reset delay time d(rst) V glitch supply voltage difference DD(gl) t supply voltage glitch pulse width ...
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... NXP Semiconductors 8.4 Device current consumption with internal pull-up and pull-down resistors The PCAL9539A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. ...
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... NXP Semiconductors 9. Limiting values Table 29. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I V output voltage O I input clamping current IK I output clamping current OK I input/output clamping current IOK I LOW-level output current ...
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... NXP Semiconductors 12. Static characteristics Table 32. Static characteristics + 1. 5.5 V; unless otherwise specified. amb DD Symbol Parameter V input clamping voltage IK V power-on reset voltage POR V HIGH-level output voltage OH V LOW-level output voltage OL I LOW-level output current OL I input current ...
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... NXP Semiconductors Table 32. Static characteristics + 1. 5.5 V; unless otherwise specified. amb DD Symbol Parameter I supply current DD I additional quiescent DD [4] supply current C input capacitance i C input/output capacitance io R internal pull-up resistance pu(int) R internal pull-down resistance input/output ...
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... NXP Semiconductors 12.1 Typical characteristics (μ 5 5 3.3 V 2 −40 −15 10 Fig 21. Supply current versus ambient temperature (μ 1.5 2.5 3 C T amb Fig 23. Supply current versus supply voltage PCAL9539A Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset ...
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... NXP Semiconductors 35 I sink (mA −40 °C amb 25 ° ° 0 1. sink (mA −40 °C amb 25 ° ° 0 2 sink (mA −40 °C 60 amb 25 °C 85 ° 0 ...
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... NXP Semiconductors 30 I source (mA −40 °C amb 25 ° ° 0 1. source (mA −40 °C amb 25 ° ° 0 2 source T = −40 °C amb (mA) 25 °C 85 ° 0 5 Fig 26. I/O source current versus HIGH-level output voltage with CCX.X = 11b ...
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... NXP Semiconductors 120 V OL (mV) 100 ( (2) 40 (4) 20 (3) 0 −40 − sink ( sink ( 1 sink ( sink Fig 27. LOW-level output voltage versus temperature PCAL9539A Product data sheet 2 16-bit I ...
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... NXP Semiconductors 13. Dynamic characteristics 2 Table 33. I C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Symbol Parameter f SCL clock frequency SCL t HIGH period of the SCL clock HIGH t LOW period of the SCL clock LOW t pulse width of spikes that must ...
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... NXP Semiconductors Table 35. Switching characteristics Over recommended operating free air temperature range; C Symbol Parameter t valid time on pin INT v(INT) t reset time on pin INT rst(INT) t data output valid time v(Q) t data input set-up time su(D) t data input hold time h(D) 14. Parameter measurement information a. SDA load configuration ...
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... NXP Semiconductors a. Interrupt load configuration START condition slave address SDA SCL INT A t v(INT) A data into ADDRESS port INT t v(INT) Pn View Voltage waveforms C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z All parameters and waveforms are not applicable to all devices ...
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... NXP Semiconductors a. P port load configuration SCL SDA Pn b. Write mode (R SCL Pn c. Read mode (R includes probe and jig capacitance measured from 0.7 v(Q) All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors SDA DUT a. SDA load configuration START SCL SDA RESET t rec(rst RESET timing C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors 15. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0.30 mm 0.8 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCAL9539A Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset maximum peak temperature ...
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... NXP Semiconductors 18. Soldering: PCB footprints Footprint information for reflow soldering of TSSOP24 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 36. PCB footprint for SOT355-1 (TSSOP24); reflow soldering PCAL9539A Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN24 package (0.105 solder land solder paste deposit solder land plus solder paste occupied area Dimensions 0.500 5.000 5.000 3.200 3.200 07-09-24 Issue date 09-06-15 Fig 37. PCB footprint for SOT994-1 (HWQFN24); reflow soldering ...
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... NXP Semiconductors 19. Abbreviations Table 38. Acronym ACPI CBT CDM CMOS ESD FET FF GPIO HBM 2 I C-bus I/O LED LSB MSB PCB POR PRR SMBus 20. Revision history Table 39. Revision history Document ID Release date PCAL9539A v.1 20121003 PCAL9539A Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... I C-bus and SMBus low power I/O port with interrupt and reset own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.1 Pointer register and command byte . . . . . . . . . 5 6.2.2 Input port register pair (00h, 01h ...