PCAL9539AHF,128 NXP Semiconductors, PCAL9539AHF,128 Datasheet - Page 12

• Manufacturer Part Number: PCAL9539AHF,128
• Description: Interface - I/O Expanders
• Manufacturer: NXP Semiconductors

Specifications of PCAL9539AHF,128

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HWQFN-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
PCAL9539A
Product data sheet
6.2.12 Output port configuration register (4Fh)
6.2.11 Interrupt status register pair (4Ch, 4Dh)
These read-only registers are used to identify the source of an interrupt. When read, a
logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0
indicates that the input pin is not the source of an interrupt.
When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt
status bit will return logic 0. A register pair write is described in
pair read is described in
Table 25.
Table 26.
The output port configuration register selects port-wise push-pull or open-drain I/O stage.
A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see
configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended
command sequence to program this register (4Fh) before the configuration registers (06h,
07h) sets the port pins as outputs.
ODEN0 configures Port 0_x and ODEN1 configures Port 1_x.
Table 27.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Interrupt status port 0 register (address 4Ch) bit description
Interrupt status port 1 register (address 4Dh) bit description
Output port configuration register (address 4Fh)
S0.7
S1.7
7
0
7
0
7
0
16-bit I
All information provided in this document is subject to legal disclaimers.
S0.6
S1.6
Rev. 1 — 3 October 2012
2
C-bus and SMBus low power I/O port with interrupt and reset
6
0
6
0
6
0
Section
S0.5
S1.5
7.2.
5
0
5
0
5
0
reserved
S0.4
S1.4
4
0
4
0
4
0
S0.3
S1.3
3
0
3
0
3
0
S0.2
S1.2
Section 7.1
PCAL9539A
2
0
2
0
2
0
Figure
ODEN1
© NXP B.V. 2012. All rights reserved.
S0.1
S1.1
1
0
1
0
1
0
and a register
6). A logic 1
ODEN0
S0.0
S1.0
12 of 48
0
0
0
0
0
0