PCAL6416AEVJ NXP Semiconductors, PCAL6416AEVJ Datasheet - Page 15

• Manufacturer Part Number: PCAL6416AEVJ
• Description: Interface - I/O Expanders 16bit I2C/SMBus IO Expander w/Interrupt
• Manufacturer: NXP Semiconductors

Specifications of PCAL6416AEVJ

• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: VFBGA-24
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders

NXP Semiconductors
PCAL6416A
Product data sheet
7.4.8 Pull-up/pull-down selection register pair (48h, 49h)
7.4.9 Interrupt mask register pair (4Ah, 4Bh)
The I/O port can be configured to have pull-up or pull-down resistor by programming the
pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up
resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that
I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no
effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
A register pair write operation is described in
described in
Table 23.
Table 24.
Interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during
system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0.
If an input changes state and the corresponding bit in the Interrupt mask register is set
to 1, the interrupt is masked and the interrupt pin will not be asserted. If the corresponding
bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted.
When an input changes state and the resulting interrupt is masked (interrupt mask bit
is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted. If
the interrupt mask bit of an input that is currently the source of an interrupt is set to 1, the
interrupt pin will be deasserted. A register pair write operation is described in
A register pair read operation is described in
Table 25.
Table 26.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Pull-up/pull-down selection port 0 register (address 48h)
Pull-up/pull-down selection port 1 register (address 49h)
Interrupt mask port 0 register (address 4Ah) bit description
Interrupt mask port 1 register (address 4Bh) bit description
PUD0.7
PUD1.7
M0.7
M1.7
Section
7
1
7
1
7
1
7
1
All information provided in this document is subject to legal disclaimers.
8.2.
PUD0.6
PUD1.6
Rev. 3 — 24 December 2012
M0.6
M1.6
6
1
6
1
6
1
6
1
Low-voltage translating 16-bit I
PUD0.5
PUD1.5
M0.5
M1.5
5
1
5
1
5
1
5
1
PUD0.4
PUD1.4
M0.4
M1.4
4
1
4
1
4
1
4
1
Section
Section
PUD0.3
PUD1.3
M0.3
M1.3
8.1. A register pair read operation is
8.2.
3
1
3
1
3
1
3
1
2
C-bus/SMBus I/O expander
PUD0.2
PUD1.2
M0.2
M1.2
PCAL6416A
2
1
2
1
2
1
2
1
PUD0.1
PUD1.1
© NXP B.V. 2012. All rights reserved.
M0.1
M1.1
1
1
1
1
1
1
1
1
Section
PUD0.0
PUD1.0
M0.0
M1.0
15 of 54
0
1
0
1
0
1
0
1
8.1.