SC16IS762IPW-F NXP Semiconductors, SC16IS762IPW-F Datasheet - Page 31

• Manufacturer Part Number: SC16IS762IPW-F
• Description: UART Interface IC I2C/SPI-UARTBRIDGE W/IRDA AND GPIO
• Manufacturer: NXP Semiconductors
• Type: RS-232 or RS-485 or IrDAr

Specifications of SC16IS762IPW-F

• Product Category: UART Interface IC
• Rohs: yes
• Number Of Channels: 2
• Data Rate: 5 Mbps
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TSSOP-28
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Factory Pack Quantity: 2500
• Part # Aliases: SC16IS762IPW,128

NXP Semiconductors
SC16IS752_SC16IS762
Product data sheet
8.17 I/O Interrupt Enable register (IOIntEna)
8.18 I/O Control register (IOControl)
This register enables the interrupt due to a change in the I/O configured as inputs. If
GPIO[7:4] or GPIO[3:0] are programmed as modem pins, their interrupt generation must
be enabled via IER[3]. In this case, IOIntEna will have no effect on GPIO[7:4] or
GPIO[3:0].
Table 28.
Table 29.
Remark: As I/O pins, the direction, state, and interrupt enable of GPIO are controlled by
the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI, DSR
pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these three
pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the state of
the DTR pin cannot be controlled by MCR[0].
As modem CD, RI, DSR pins, the status at the input of these three pins can be read from
MSR[7:5] and MSR[3:1], and the state of the DTR pin can be controlled by MCR[0]. Also,
if modem status interrupt bit is enabled, IER[3], a change of state on RI, CD, DSR pins will
trigger a modem interrupt. The IODir, IOState, and IOIntEna registers will not have any
effect on these three pins.
Bit
7:0
Bit
7:4
3
2
1
0
Symbol
IOIntEna
Symbol
reserved
SRESET
GPIO[3:0] or
RIB, CDB,
DTRB, DSRB
GPIO[7:4] or
RIA, CDA,
DTRA, DSRA
IOLATCH
IOIntEna register bits description
IOControl register bits description
All information provided in this document is subject to legal disclaimers.
Dual UART with I
Rev. 9 — 22 March 2012
Input interrupt enable.
These bits are reserved for future use.
Description
Description
Software Reset. A write to this bit will reset the device. Once the
device is reset this bit is automatically set to logic 0.
This bit programs GPIO[3:0] as I/O pins or as modem pins.
This bit programs GPIO[7:4] as I/O pins or as modem pins.
Enable/disable inputs latching.
0 = a change in the input pin will not generate an interrupt
1 = a change in the input will generate an interrupt
0 = I/O pins
1 = GPIO[3:0] emulate RIB, CDB, DTRB, DSRB
0 = I/O pins
1 = GPIO[7:4] emulate RIA, CDA, DTRA, DSRA
0 = input value are not latched. A change in any input generates an
interrupt. A read of the input register clears the interrupt. If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.
1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.
SC16IS752; SC16IS762
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
© NXP B.V. 2012. All rights reserved.
31 of 60