C8051F555-IMR Silicon Labs, C8051F555-IMR Datasheet - Page 121
C8051F555-IMR
Manufacturer Part Number
C8051F555-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB CAN2.0 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F556-IMR.pdf
(302 pages)
Specifications of C8051F555-IMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2
SFR Address = 0xF7; SFR Page = 0x00 and 0x0F
Name
Reset
Bit
7:3
Type
2
1
0
Bit
Unused
PREG0
PCAN0
Name
PMAT
R
7
0
Read = 00000b; Write = Don’t Care.
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
CAN0 Interrupt Priority Control.
This bit sets the priority of the CAN0 interrupt.
0: CAN0 interrupt set to low priority level.
1: CAN0 interrupt set to high priority level.
Voltage Regulator Dropout Interrupt Priority Control.
This bit sets the priority of the Voltage Regulator Dropout interrupt.
0: Voltage Regulator Dropout interrupt set to low priority level.
1: Voltage Regulator Dropout interrupt set to high priority level.
R
6
0
R
5
0
Rev. 1.1
R
4
0
Function
R
3
0
C8051F55x/56x/57x
PMAT
R/W
2
0
PCAN0
R/W
1
0
PREG0
R/W
0
0
121
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