C8051F555-IMR Silicon Labs, C8051F555-IMR Datasheet - Page 291

• Manufacturer Part Number: C8051F555-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB CAN2.0 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F555-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

SFR Definition 26.2. PCA0MD: PCA Mode
SFR Address = 0xD9; SFR Page = 0x00
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
Name
Reset
Bit
3:1
Type
7
6
5
4
0
Bit
CPS[2:0] PCA Counter/Timer Pulse Select.
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
WDLCK
Unused
WDTE
Name
CIDL
ECF
CIDL
R/W
7
0
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Watchdog Timer Enable
If this bit is set, PCA Module 5 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 5 enabled as Watchdog Timer.
Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Read = 0b, Write = Don't care.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
WDTE
R/W
6
1
WDLCK
R/W
5
0
Rev. 1.1
R
4
0
Function
R/W
3
0
C8051F55x/56x/57x
CPS[2:0]
R/W
2
0
R/W
1
0
ECF
R/W
0
0
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